New dual-loop topology for ring VCOs based on latched delay cells

Abstract

This paper presents an enhancement to the dual-loop topology often used to increase the maximum frequency of oscillation of voltage controlled ring oscillators (VCROs). It can be employed to practically all VCROs built with delay cells which comprise cross-coupled latches. The standard implementation of the second feedback loop implies introducing additional transistors within each delay cell. The proposed topology avoids adding components to the main delay cells; instead, the transistors which implement the cross-coupled latch within each cell are connected outside their cell, so that they also help realize the second oscillator loop. Essentially, instead of being driven by the outputs of its own delay cell, each latch is driven by the outputs of a delay cell placed ahead of it within the ring. The proposed topology is illustrated by two examples, that is, two dual-loop VCROs implemented with different types of delay cells. The first example is presented in detail: starting from the single-loop VCRO we derived the standard dual-loop version, then the proposed topology. These versions were designed in a standard 180nm CMOS process considering two scenarios: first, the VCROs were sized individually to operate at the same frequency (2.4GHz) and to yield similar phase noise values; second, they were implemented by using same sizes for corresponding transistors within their delay cells. These experiments proved that the new topology provides a very significant power reduction when operating at the same operating frequency as the standard topologies or yields a higher operating frequency than the standard topologies when burning the same amount of power. To demonstrate the generality of this approach a second example of dual-loop VCROs, based on a more complex type of delay cell, was presented briefly.