Neuron Network with a Synapse of CMOS transistor and Anti-Parallel Memristors for Low power Implementations

Abstract

The bio-mimetic structure of a neuron is taken into account for utilizing the electrophysiological data. These neuron circuits are entertained for the use in digital computers. At the end of Moore’s law, conventional technology is striking different difficulties, such as power consumption, area utilization, and energy efficiency. To conquer these hurdles, a nanoscale, the nonvolatile memristor used in the proposed neuron modified from the refined AH neuron. Synapses are also built using anti-parallel memristors. These neurons and synapse are joined together such that the performance metrics are analyzed the energy consumption is reduced by 89.656%. Besides, power consumption is limited by 37.568% and the spike frequency is measured as 10.263[Formula: see text]kHz when compared with the traditional CMOS synapse connected with the proposed neuron. Moreover, the measured energy per spike is 3.37[Formula: see text]fJ. The implementation of the neuron network is done by 45[Formula: see text]nm technology.