Near-future perspectives for Si and Si 1−yGe y bipolar transistors

Abstract

The performance limits of self-aligned npn Si-BJTs and SiGe-HBTs are investigated for different types of processing. Using a one-dimensional drift-diffusion equation solver, device simulations are carried out for different doping and germanium profiles. From these simulations network parameters are extracted, which are used as input data for the SPICE-simulation of CML ring oscillators. In addition to one verification profile, three different types of processing are considered, which are designed to give the near-future performance limits of both Si and SiGe bipolar transistors: The first one is a profile as obtained by ‘conventional’ processing utilizing implantation and diffusion. The second one has a heavily doped base and a small, lightly doped emitter region, as might be realizable by epitaxial deposition of in-situ doped layers. The third one is similar to the second one, but uses a Si 0.8Ge 0.2/Si-strained base. The simulations show that CML gate delay times of approx. 15 ps, 10 ps and 7 ps, respectively, are realizable with these profiles.