Nanoelectronic SET-based core for network-on-chip architectures

Abstract

Nanoelectronics is a very promising step the world of electronics is taking. It is proved to be more efficient than the microelectronic approaches currently in use, mainly in terms of area and energy management. A Single-Electron Transistor (SET) is capable of confining electrons to sufficiently small dimensions, so that the quantization of both their charge and their energy is easily observable, making the SET's quantum mechanical devices. These features should allow building chips with a number of devices orders of magnitude greater than indicated by the roadmap still respecting area and power consumption restrictions. In this sense, Tera Scale Integrated (TSI) systems can be feasible in the future. A digital module, such as an arithmetic logic unit, completely implemented with SETs has already been proposed and validated by simulation. In this work a completely SET based network-on-chip (NoC) nanoelectronic core is proposed. Furthermore, a simple NoC architecture based on that nanoelectronic core is also evaluated. It is shown that the SET-based NoC has a promising performance considering parameters such as power consumption, area and clock frequency. A simple comparison of mesh NoC chip prototypes is shown.