N-Type Dual Vertical C-Shaped-Channel Nanosheet FETs with Ultra-Thin Channels for High Performance Logic Application

Shallow trench isolation (STI) induced mechanical stress affects the device behavior in the advanced complementary metal oxide semiconductor (CMOS) technology. This article presents how to use an optimal STI process to reduce transistor mismatch and leakage current induced standby current in static random access memory (SRAM). The STI induced mechanical stress affects the device behavior in the advanced CMOS technology. The optimized STI process can reduce junction and bulk leakage that occurs on the STI sidewall due to STI compressive stress enhancing boron diffusion and increasing junction electric field of STI sidewall resulting in band-to-band-tunneling (BTBT) degradation. An obvious decrease in BTBT occurs on STI edge sidewall that is observed by using the optimized STI process. Meanwhile, the optimized STI process has better length of diffusion effect. Moreover, the optimized STI process can improve the parasitic device at STI edge because of smaller divot. Since random fluctuation of channel dopant and process induced device mismatch are major considerations in SRAM cell, we examine STI sidewall boron dopant diffusion effect on SRAM due to BTBT increasing exponentially with increasing doping concentration in the P-well of negative metal oxide semiconductor field effect transistor. The mismatch of passing gate of SRAM and Vcc_min can also be improved by leakage reduction from the optimized STI process due to improved random dopant fluctuation.

Two-dimensional (2D) transition metal dichalcogenides (TMDs) have emerged as a first-rate candidate for post-silicon channels in field-effect transistors (FETs), particularly in the context of monolithic three-dimensional (M3D) integration. Despite the recent synthetic advances including industry-compatible wafer-scale production, they have predominantly been prepared on the ultra-flat, non-processed surfaces, limiting device architectures to outdated planar FETs and geometrically restricting their versatile applications. Integrating 2D semiconductors into 3D device architectures currently presents two significant challenges: i) stackablity, and ii) scalablility. While 2D material-based FETs have been primarily limited to traditional planar devices structures, their applications to vertically integrated 3D devices have been hindered by low-fidelity transfer method which is certainly challenging in conformally and controllably transferring atomically thin materials onto steep sidewalls. Here, we report a directly growth-and-fabrication approach enabling the dimensional transition from 2D planar FETs to a 3D vertical-channel FETs (VCFETs) through the atomically conformal direct growth of monolayer (ML) MoS2 onto the pre-fabricated VCFET structures (Fig. 1A). Leveraging the inherently anisotropic in-plane growth kinetics and precisely controlled supersaturation based on metal-organic chemical vapor deposition, we achieved 100% step coverage even with sub-1-nm channel thickness without compromised crystallinity along an exceptionally high aspect ratio exceeding 15,000 (Fig. 1B). We proved that monolayer MoS2 grown along the SiO2 vertical sidewall is a single crystal by comparing the angles of the selected-area electron diffraction (SAED) pattern in transmission electron microscope (TEM) at the three vertices of MoS2 (Fig. 1C). Fig. 1D shows a cross-sectional scanning transmission electron microscope (STEM) image of the VCFET with and spatial distribution of each element was also identified by energy dispersive X-ray spectroscopy (EDS) mapping images, and it convincingly suggests that atomically conformal monolayer MoS2 was indeed integrated without discontinuity and void even along a steep trench edge (Fig. 1D). Fig. 1E illustrates the unit device schematic of the monolayer MoS2 VCFET. The experimental and simulated transfer characteristic (I DS-V GS) of VCFET with vertical monolayer MoS2 well-coincide each other, showing the subthreshold swing (SS) of 77mV·dec−1 and the ON/OFF ratio of 108 under a drain-to-source bias (V DS) of 1V (Fig. 1F). Output characteristic (I DS-V DS) indicates the change in conductivity of the MoS2 channel by regulating the V G at steps of 1V from −2V to 5V (Fig. 1G). To evaluate device-to-device variation and statistic distribution of their performance, electrical characterization of the 7×7 VCFETs array was performed and their I DS-V GS curves under V DS = +1V exhibited the excellent reproducibility (Fig. 1H). Fig. 1I shows low OFF-state current density of 10−13A∙μm−1 at all devices in our monolayer MoS2 VCFET array, which is 10 times lower than the International Roadmap for Devices and Systems (IRDS) 2028 low-standby power device requirement (~10−12A∙μm−1). Sentaurus technology computer-aided design (TCAD) simulations for monolayer MoS2 VCFET were performed to investigate the electric field distribution of ON-state (V GS = +5V) and OFF-state (V GS = −2V), respectively (Fig. 1J-K). To demonstrate how electron concentration changes in monolayer MoS2 at the sidewall control the switching operation of the transistor, we fabricated a multi-gate VCFET (Fig. 1L). The additional terminals, a modulation gate (MG) and a back gate (BG), facilitate to form an effective gate length near the control gate (CG), enabling a switching behavior of the transistor. The MG screens the electric field toward the top of the trench from the CG, maintaining the electron concentration of the monolayer MoS2 on the top region of the trench and restricting switching operation to monolayer MoS2 on the vertical sidewall. I DS-V CG curve was obtained by applying the CG bias (V CG) and the BG bias (V BG) of +30V with the floated MG bias (V MG) (Fig. 1M). The fabricated multi-gate VCFET further validated the superior sidewall-gate controllability of the ultrathin monolayer MoS2 channel on the vertical sidewall, with aid of TCAD simulation. In the ON-state (V CG = +2.5V), the MG screens electric field generated by CG, allowing the electric field of CG to accumulate electrons effectively along the vertical monolayer MoS2 sidewall, as shown in Fig. 1N. in the OFF-state (V CG = −2.5V), the electric field contour plot reveals that the electric field from the CG does not reach the top region of trench due the MG, while forming a strong electric field near the CG, leading to deplete the MoS2 channel (Fig. 1O). Our work establishes a tailored pathway for the bespoke monolithic integration of ML semiconductors, positioning them as viable channels for high-density, high-performance computational device. Our integration strategy is undisputed pathway for M3D integration and usher in a new era of atomic-level fabric. Figure 1

Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

Radiation-induced single event upsets (SEUs), or soft errors, have become a dominant factor in the reliability degradation of nanoscale memories. In this paper, based on the SEU physics mechanism, and reasonable layout-topology, a novel soft error hardened memory cell is proposed in 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. The design comparisons for several hardened memory cells in terms of access time (read access time and write access time), power consumption, and layout area are also executed. The main advantage of the proposed cell is that it can provide 100% fault tolerance, which is very useful for memory applications in severe radiation environments. Furthermore, Monte Carlo simulations are carried out to evaluate the effects of process, voltage, and temperature (PVT) variations. From simulations, we confirmed that the proposed cell has exhibited a sufficient multiple-node upset tolerance capability even under PVT variations.

Polysilicon diodes used in sub-quarter-micron complementary metal oxide semiconductor (CMOS) technologies are characterized by transmission line pulse (TLP) measurement to investigate device characteristics in a high-current regime. The second-breakdown current (It2) of the polysilicon diode shows good linear dependence on the device junction perimeter. When the polysilicon diodes are connected in a stacked configuration for reducing parasitic capacitance, the stacked polysilicon diodes show no degradation in electrostatic discharge (ESD) robustness compared with a single polysilicon diode. Such CMOS process-compatible polysilicon diodes have been successfully used as on-chip ESD protection devices for GHz radio-frequency (RF) circuits.

Low‐voltage design is a challenge for Gilbert cell‐based mixers due to stacking transconductance and switching stage. This work addresses this issue by proposing a design of a low‐voltage down‐conversion mixer for band #1 of multiband orthogonal frequency division multiplexing (MB‐OFDM) system in 180 nm complementary metal oxide semiconductor (CMOS) technology. The mixer is tuned at band #1 at RF frequency of 3.432 GHz and IF frequency of 264 MHz. The proposed mixer uses folded cascode connection of LO and RF in order to increase headroom and to reduce the DC supply voltage for low‐voltage operation. Common gate configuration is used at RF transconductance stage to enhance the input bandwidth of the mixer. RF and LO ports are matched to 50 Ω using differential T and LC matching, respectively. The resistive source denegation technique is used to linearize transconductance with respect to the bias point. The common source stage is used at the IF port as a buffer cum matching circuit it. The simulation results of the mixer show the maximum conversion gain of 9.76 dB, 1 dB compression point (P1dB) of ‐16.25 dBm, the third‐order input intercept point (IIP3) of ‐4.70 dBm, an SSB noise figure of 9.036 dB, and S11of ‐19.490 dB at the supply voltage of 1.2 V. Excluding off chip components, proposed mixer records an active area of 926.35 μm2.

Complementary metal oxide semiconductor (CMOS) technology is one of the leading fabrication technologies of the semiconductor integrated-circuit industry. We have discovered features inherent in the standard CMOS fabrication process that lend themselves to the manufacturing of micromechanical structures for sensor applications. In this paper we present an unconventional layout design methodology that allows us to exploit the standard CMOS process for producing microbridges. Two types of microbridges, bare polysilicon microbridges and sandwiched oxide microbridges, have been manufactured by first implementing a special layout design in an industrial digital CMOS process, followed by a postprocessing etching step.

Quantum-dot cellular automata (QCA) nanotechnology is a suitable replacement for the widely accepted complementary metal oxide semiconductor (CMOS) technology. CMOS technology faces the issues of high-leakage current and non-scalability in the ultra-deep submicron (ultra-DSM) regime. It motivates the researchers to explore new technologies for further advancement of the field. QCA nanotechnology is energy-efficient technology and it overcomes the issues of CMOS technology in ultra-DSM regime. In this paper, a novel 3-input XOR structure is presented using QCA nanotechnology. The full adder and the full subtractor circuits based on the 3-input XOR gate are developed. A circuit for the full adder/subtractor nanostructure is proposed in the paper. All the proposed designs are optimal, fault-tolerant and single-layered. The proposed full adder contains only 21 QCA cells, while 22 QCA cells are required for the proposed full subtractor. The proposed full adder/subtractor structure consists of only 30 QCA cells. The proposed designs are compared with the existing designs for the number of QCA cells, total cell area, total covered area, area utilization, clock latency, QCA layout cost, and crossover requirement. The energy-efficient behaviour of the proposed circuits is calculated using the QCA Designer-E and the QCA Pro tools.

CHAPTER 2 - Fundamentals of CMOS design

Study of resistive random access memory based on TiN/TaOx/TiN integrated into a 65 nm advanced complementary metal oxide semiconductor technology

As conventional CMOS scaling is reaching its physical limits with ever more constraining design restrictions, new device architectures are being explored as potential fin-field-effect-transistor (finFET) replacements for future technology nodes. Among the various options, vertically stacked lateral nanosheet (NS) FETs with a gate-all-around (GAA) configuration are considered the most promising and mature candidates to use next to help preserve the overall power-performance logic roadmap [1-5]. These devices offer improved electrostatics control and allow additional design flexibility for applications-driven power and performance tuning. Indeed, the possibility to fabricate on the same wafer varying NS widths, enabling devices with a wide range of effective widths (Weff), is one of their key attractive features. Wider GAA NS FETs enable higher drive current (ION) gains. However, as shown in ref. [2], these can be compromised for shrinking gate length (Lgate) due to degraded electrostatics, e.g., worst subthreshold slope (SS) values. As for narrower NS FETs, despite their lower ION, they also correspond to decreased channel, overlap and fringe capacitance values. In addition, as extension and contact resistances can also depend substantially on the NS cross-sectional areas [2], several trade-offs will ultimately determine the NS device configuration that best fulfills the requirements for a given application.Fabrication-wise, GAA lateral NS FET devices can be regarded as a natural extension of finFETs sharing many of their building blocks. Some of the key process steps are illustrated in Fig. 1, wherein Si/SiGe multi-layers are epitaxially grown prior to fin patterning to form vertically stacked silicon lateral NS. At replacement metal gate (RMG) module, prior to gate stack deposition, NS are released by implementing a selective removal of the SiGe from the Si/SiGe multi-layer fins. This is a key step, critical for preserving the integrity of the Si channels in terms of shape, dimensions and quality of the NS surfaces. Another crucial step occurs earlier on in the flow at STI module, where insertion of a thin nitride liner prior to STI oxide fill and densification anneal can prevent Si/SiGe fin oxidation and Ge diffusion. Such processing helps preserving the fins profile while also protecting them from irreversible strain modifications [4]. Fig. 2 shows an example of a TEM image from a device built with two vertically stacked NS. The well-preserved shape of the NS also enables implementation of a highly uniform and scaled gate stack on all NS surfaces with smooth interfaces [6]. This is of increased importance for scaled GAA NS FETs where reduced vertical distance between the stacked NS is required to minimize device parasitics.Another type of GAA NS transistors are the vertical NS (VNS) FETs for which Lgate is defined vertically and hence can be relaxed without impacting the device footprint. Representing a more disruptive technological transition, both in terms of device fabrication and circuit layout design, these devices have nevertheless the potential to open up new scaling paths and enable denser, better performing circuits, e.g., for SRAM (as the cell transistors) or MRAM (as the cell selector) memories [7,8].Fig. 3 illustrates some of the key steps followed to implement an RMG module in GAA vertical nanowire (VNW) or VNS FETs. A layout dependence for some of the processes used in this block can be seen to impact DC characteristics such as VT, ION. The VNW/VNS doping vs. wire/sheet dimensions also needs to be accounted for in case of junctionless devices [8, 9]. RMG can also be used to enable a scheme that boosts the mobility in vertical channels via process-induced stress as described in Fig. 4 for NMOS. Here, a SiGe stressor is epitaxially grown around the Si channel after spacers formation. This stressor is removed at RMG module, after dummy gate removal, with stress memorization into its surroundings enabled by the fact that the layer encapsulating the top of the pillars remains connected (at some places) to the bottom isolation layer. Stress and ballistic current simulations indicate that up to ~19% higher ION can hence be obtained [8].

Interface traps in the sub-3 nm technology node: A comprehensive analysis and benchmarking of negative capacitance FinFET and nanosheet FETs - A reliability perspective from device to circuit level

A novel transport model for the subthreshold mode of double-gate MOSFETs (DGMOSFETs) is proposed in this paper. The model enables the analysis of short-channel effects (SCEs) such as the subthreshold swing (SS), the threshold-voltage rolloff, and the drain-induced barrier lowering. The proposed model includes the effects of thermionic emission and the quantum tunneling of carriers through the source-drain barrier. An approximative solution of the two-dimensional Poisson equation is used for the distribution of the electric potential, and the Wentzel-Kramers-Brillouin approximation is used for the tunneling probability. The model is verified by comparing the SS with numerical simulations. The new model is used to investigate the subthreshold characteristics of a DGMOSFET having the gate length in the nanometer range with an ultrathin gate oxide and channel thickness. The SCEs degrade the subthreshold characteristics of DGMOSFETs when the gate length is reduced below 10 nm, and any design in the sub-10-nm-regime should include the effects of quantum tunneling.

Introduction Nowadays, the scaling of silicon very large-scale integration(VLSI) technologies has reached channel thicknesses of 7nm. However, further downscaling becomes increasingly difficult as the gate electrostatics require a substantial reduction of the channel thickness to about a fourth of the gate length. As a result, the actual gate length of high-performance(HP) FETs at the current state-of-the-art amounts to 16nm and is projected to stall at 12nm for the 1.5nm node and the following nodes, according to the International Roadmap for Devices and Systems(IRDS)[1]. For these nodes, two-dimensional(2D) materials could have the potential to replace silicon as the channel material. They can maintain sizable mobilities at atomic thicknesses, thus providing enhanced gate control in stacked channel nanosheet transistor structures[2]. Even though FETs based on 2D materials hold the promise to serve as FETs at the front end of the line, numerous challenges still need to be overcome. Downscaling Dimensions For ultra-scaled device designs, 2D materials can be used as a channel in stacked nanosheet FETs. In such a structure, the 2D material is gated from both sides, as depicted in Fig.1(a). By stacking multiple double-gated channels on top of each other, the required on-current density of around 1mA/μm can be achieved[3]. The first experimental demonstrations have achieved sub-5nm gate lengths[4] or, in a different design, a gate pitch of only 42nm[5], meeting the requirements for the 1.5nm node. While these prototypes show that 2D FETs can be scaled down, they have been fabricated in a laboratory. Many challenges must be overcome before such small devices can be fabricated in industry-compatible batch processes which require a high yield and low variability. Contact Engineering In order to enable sufficiently high on-current densities, small contact resistances to 2D semiconductors are required, which are inhibited by the formation of Schottky barriers at the metal to semiconductor interface. Schottky contacts to 2D materials are so prevalent because there is, on one side, a lack of stable doping schemes, and on the other side, pronounced Fermi-level pinning at the metal-to-semiconductor interface. Semi-metallic bismuth contacts can provide low-resistive contacts to n-type MoS2 FETs, as the bismuth suppresses the metal-induced gap states which pin the Fermi-level[6]. This way, a small contact resistance of 123Ωμm has been achieved, reaching the IRDS limit for the 1.5nm node. While comparable results have been realized for antimony contacts to n-type FETs, low-resistive contacts to p-type FETs are more challenging. Gate Stack Design A good gate stack for 2D FETs must provide excellent gate control while maintaining small gate leakage currents, which requires a capacitive equivalent thickness(CET) smaller than 0.9 nm. At these small CETs, a small gate leakage can only be obtained with a high-dielectric constant gate insulator and sizable band offsets, rendering some insulators, e.g. hexagonal boron nitride, unsuitable. Simultaneously, the gate insulator should form a van-der Waals interface with the 2D semiconductor, as otherwise, interface traps degrade the carrier mobility and the sub-threshold slope[7]. Charge traps within the insulator are the root cause of the limited stability and reliability of 2D FETs, as seen by a large hysteresis in the transfer characteristics or in pronounced Bias Temperature Instabilities(BTI). The electrical stability can be improved, if the defect bands in the gate insulator are energetically far away from the semiconductor’s conduction and valence band edges, see Fig.1(b)[8]. Conclusions Despite all the progress achieved within the last decade, the challenges for VLSI integration of 2D materials are enormous. First, stacked 2D FETs with scaled dimensions still need to be realized at an industrial scale. Second, despite low contact resistance demonstrations for n-type FETs, the resistances for p-type FETs are one order of magnitude too high. Finally, one of the most serious obstacles is identifying a suitable gate stack. Even though promising combinations of insulators to semiconductors have been suggested, like Bi2O5Se/Bi2O2Se, CaF2/MoS2 or SrTiO3/MoS2, it is at the moment unclear, which of them provides the best performance. Acknowledgments The authors thank for funding from the European Research Council under grant agreement no. 101055379.

A fabrication technique for a vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) with a standing-up ultrathin channel (UTC) and self-aligned source and drain (S/D) is proposed. A 20nm thick vertical UTC with low channel thickness fluctuation was formed on a (110)-oriented Si substrate using orientation-dependent wet etching. The top and bottom S/D were self-aligned to the DGs by using a combination of ion implantation and solid-phase diffusion. The fabricated vertical DG MOSFETs revealed that the channel thickness less influences the threshold voltage. Furthermore, a low sub-threshold slope of 68.8mV/decade was achieved with a channel thickness of 20nm.