多層基板の熱変形挙動の予測およびそのパッケージの反り解析への適用

Abstract

In electronic packages such as a BGA package, decrease of package warpage in the temperature range where the package is used is a key issue in order to enhance the reliability of solder connection and to reduce the number of defective packages. If we can predict the package warpage accurately in the design stage of electronic packaging by using a simulation method, we can make use of such a prediction to enhance the reliability of electronic packaging. We need the material properties of silicon chip, molding resin and printed circuit board (PCB) used as a substrate to predict the package warpage. Among them, PCBs have multi-layered structures, and each layer has a complicated structure such as fine and high density wiring pattern. In the present study, we propose a method for predicting the thermal deformation of PCB using a finite element viscoelastic analysis, in which the complicated structure of each layer in PCB is taken into account. The apparent coefficient of thermal expansion (CTE) for PCB calculated from the proposed method is compared with the experimental results to show the effectiveness of the proposed method. Furthermore, it is shown that the warpage of a package consisting of a silicon chip and a substrate (PCB) can be predicted using the apparent CTE of PCB.