Multiple Cell Upsets as the Key Contribution to the Total SER of 65 nm CMOS SRAMs and Its Dependence on Well Engineering

Abstract

Neutron and alpha SER test results are presented for two SRAMs processed in a commercial 65 nm CMOS technology. Devices with the commonly used triple well option have higher rates of multiple cell upsets (MCU) and therefore higher SER. The same behavior is reported for older technologies from 180 nm to 65 nm. Full 3-D device simulations on 65 nm SRAM cells quantify the amplification of the charge collection with the usage of triple well and frequency of well contacts.