Multigate-Cell Stacked FET Design for Millimeter-Wave CMOS Power Amplifiers

Abstract

To increase the voltage handling capability of scaled CMOS-based circuits, series connection (stacking) of transistors has been demonstrated in recently reported mm-wave power amplifiers. This paper discusses the implementation of stacked CMOS circuits employing a compact, multigate layout technique, rather than the conventional series connection of individual transistors. A unit multigate FET is composed of a single transistor with one source and drain and multiple (four) gate connections. Capacitances are implemented in a distributed manner allowing close proximity to the individual gate fingers using metal layers available within the CMOS back-end-of-line (BEOL) stack. The multigate structure is demonstrated to decrease parasitic resistances and capacitances, and has better layout for heat-sinking. The unit cell is replicated through tiling to implement larger effective gate widths. Millimeter-wave power amplifiers using the multigate-cell are presented which operate over the 25–35 GHz band and achieve 300 mW of saturated output power and peak power-added efficiency (PAE) of 30% in 45 nm CMOS SOI technology. To the authors’ knowledge, the output power is the best reported for a single stage CMOS power amplifier that does not use power-combining for this frequency range.