Modeling of thermal damage and residual stress in slicing of silicon wafers using wire-electrical discharge machining: Comparison with experiments

Abstract

Wire electrical discharge machining (wire-EDM) is a potential technique to fabricate high-quality ultra-thin silicon (Si) wafers. However, its universal integration at the industrial scale remains impeded by the inherent limitation of induced thermal damage and residual stress. It is understood that the process parameters play a significant role in determining these subsurface damages. Therefore, a single-pulse thermal model accounting for plasma heating through a surface heat flux is developed in the present study. The applied heat flux encompasses the heat transferred to the workpiece through sparking during pulse on-time. The heat flux post spark incorporates the heat dissipation via expanding plasma channel. The governing equations of the 2D computational model are solved using the finite element method (FEM) in ABAQUSTM. The proposed model is in good agreement with the experimental results of thermal damage (10 %–13 %), peak residual stress (5 %–10 %), and residual stress damage depth (15 %–20 %). It is observed the wire-EDM slicing of silicon wafers can induce thermal damage of 10–34μm, peak residual stress of 95–180 MPa, and residual stress damage depth of 13.6–55μm. The open voltage is found to have a more significant influence on thermal damage and residual stress than pulse on-time. The model reveals that thermal damage depth could be reduced to as low as 10μm, residual stress damage depth up to 13.6μm, and peak residual stress up to 95 MPa.