Modeling and Suppression of Parasitic Oscillations in Enhanced‐Mode GaN HEMT Circuits

The false turn-on induced by the gate loop parasitic and Miller capacitance during the fast switching transient of SiC MOSFET leads to increased switching loss, circuit oscillation and even shoot-through. Using a negative OFF-state gate voltage VGS- off can effectively mitigate the false turn-on issue. However, this approach also raises the magnitude of negative gate voltage spikes that occur during the fall of VDS, leading to unwanted negative gate overstress. In this work, a simple GaN-HEMT-based gate clamping circuit (GCC) is designed for SiC MOSFET negative gate voltage spike clamping. Thanks to the fast switching speed of GaN HEMT, GCC can clamp the negative spike effectively even at a high slew rate of VDS (120 V/ns), protecting the gate from overstress when negative VGS-off is applied to suppress false turn-on. © 2023 IEEE.

Gallium nitride high electron mobility transistor (GaN HEMT) is liable to gate false turn-on problem when the gate crosstalk voltage exceeds its threshold voltage in the widely adopted phase-leg topology due to its low threshold voltage and high switching speed. Without considering the gate loop stray inductance, gate internal resistance, nonlinearity of parasitic capacitances and power loop stray parameters, traditional false turn-on analytical method is insufficient to support accurate analysis. And it has been found that GaN HEMT gate-source parasitic capacitance <inline-formula> <tex-math notation="LaTeX">$C_{\mathrm {gs}}$ </tex-math></inline-formula> previously assumed constant is otherwise highly nonlinear and has strong impacts on the gate crosstalk voltage. This paper has measured <inline-formula> <tex-math notation="LaTeX">$C_{\mathrm {gs}}$ </tex-math></inline-formula> by vector network analyzer and constructed an accurate nonlinear model of <inline-formula> <tex-math notation="LaTeX">$C_{\mathrm {gs}}$ </tex-math></inline-formula>, based on which an accurate GaN HEMT behavior model is further fulfilled. The accuracy of the proposed behavior model has been verified by large amounts of experiment results. The proposed GaN HEMT model is used to accurately calculate gate crosstalk voltage and switching losses. Besides, false turn-on induced extra loss has been calculated and is adopted as a criterion to evaluate the severity of false turn-on and optimal design method for false turn-on suppression has been detailed further.

Negative spikes followed by positive ones in the loop voltage signal during the discharge are observed in the Aditya Tokamak [S. B. Bhatt et al., Indian J. Pure Appl. Phys. 27, 710 (1989)]. These spikes are always accompanied by hard x-ray bursts caused by sudden loss of runaway electrons. The observed growth of m=3 mode seemed responsible for the losses of localized beams of runaway electrons (Eγ∼1–5 MeV) from the plasma region around q=3 magnetic surface. The movement of these runaway electrons during their extraction from inside the plasma induces both positive and negative electric fields at those locations. In this paper, a one-dimensional toroidal electric field diffusion model is used to estimate the induced electric field at the plasma boundary, which matches quite well with the observed spikes in loop voltage in both magnitude as well as its temporal evolution.

Considering the high switching speed characteristics of silicon carbide power devices and the fact that parasitic parameters cannot be ignored, the crosstalk phenomenon of SiC MOSFET power modules under traditional driving methods is more significant than that of silicon-based modules. Existing crosstalk suppression schemes generally have the three contradictions of increased switching delay, increased switching loss and increased control complexity, which makes it difficult to effectively balance the synergistic relationship between positive and negative bidirectional crosstalk spike suppression and dynamic characteristic optimization. This paper proposes a bidirectional crosstalk suppression gate drive based on a low-impedance loop combined with a multi-level turn-off gate voltage. By establishing a time-domain analytical model of the crosstalk generation mechanism, the physical limitations of the active gate control strategy in negative crosstalk suppression are revealed. A dynamic gate voltage reconstruction mechanism is introduced, and the turn-off gate voltage is adaptively adjusted through a self-driven auxiliary network to achieve effective suppression of negative crosstalk. Experimental verification shows that the negative crosstalk peak is reduced by 2.33V, which can achieve a 36% reduction. Secondly, considering the coupling effect of the positive spike by the auxiliary network, the low-impedance path formed by the transistor auxiliary current branch is used to achieve decoupling, which can limit the positive crosstalk voltage to a safe threshold range. The proposed driving method directly uses the gate-source intrinsic voltage as the control signal and can be implemented without additional isolation circuits. The experiment is based on PSpice simulation and double pulse test of 1.2KV/80-A silicon carbide module to compare and evaluate the crosstalk suppression capability of the driving method.

Because SiC MOSFET-based zero-voltage switching (ZVS) power converter circuits provide high-speed switching, high power density and high efficiency can be achieved. However, an undesired negative spike is formed at the gate-source voltage owing to the crosstalk phenomenon in leg structures, such as half-bridge switch configurations, during high-speed switching. Additionally, ringing voltage occurs owing to resonance between the snubber capacitor and the common source inductance of the SiC MOSFET. Because SiC MOSFETs have a lower gate voltage rating than conventional Si devices, it is essential to reduce the negative spike and ringing voltages to ensure reliability. In this paper, the gate driver circuit is proposed for reducing the negative spike and ringing voltages of the gate-source in ZVS circuits. Because the proposed gate driver circuit provides an effective impedance path for each section through an active switch, a stable driving voltage range of the gate-source can be achieved. To verify the proposed gate driver circuit, an accurate simulation model of the 3-pin SiC MOSFET package is proposed, and the validity of the proposed model is verified through comparison of the simulated waveforms with experimental waveforms. The performance of the proposed gate driver circuit is verified through PSpice simulation.

This DNS study is focused on the structure of turbulence in a boundary layer. First, it is not appropriate to call the turbulent flow as a “random” motion. Any mean flow like Blasius solution, which is a Navier-Stokes solution, added by white noise or random perturbation would be rejected by Navier-Stokes equations and the perturbation will be damped quickly. The governing Navier-Stokes equations only accept certain structured flows and turbulent flow is a solution that the Navier-Stokes equations can accept. Turbulent flow is not random solutions because the governing Navier-Stokes equations do not allow. The DNS finding shows turbulence is built up by organized “vortex packages” which can be accepted by Navier-Stokes equations. Since these packages keep moving around, it would make a fake impression that the flow is “random”. The so-called “intermittence” really represents the motion of the “vortex packages”, self-motion and relative-motion, and the packages never disappear or destroyed periodically in the turbulent flow. The package itself must have certain structure to generate a variety of different size vortices and keep the energy transport from high energy inviscid flow to the viscous boundary layer bottom. The small size vortices need energy to survive to balance the viscous dissipation. This paper will provide a detailed observation and analysis on the formation of these vortex packages. Unfortunately, the “vortex breakdown” and “energy cascade” proposed by Richardson and accepted by Kolmogorof are never observed by any DNS or experiment. Following observations have been made by our recent DNS (Chen et al. 2011; Liu et al, 2010 a, 2010b, 2010d, 2011a, 2011b; Lu et al, 2011a, 2011b 2012). First, the large multiple vortex structure is studied including the vortex legs (rotation cores), first vortex ring, multiple vortex rings, stretch of the rings, secondary vortex and tertiary vortex. Here, a 2 λ visualization method developed by Jeong et al (1995) is used. Second, the sweeps and ejections induced by the large vortex rings are found very important. They produce low speed zones (negative spikes) in the upper boundary layer and high speed zones (positive spikes) near the bottom and further generate high shear layers. These multiple level high shear layers will further generate smaller vortices of different size at different level due to the shear layer instability. Therefore, the small vortices (and turbulence) are not generated by “vortex breakdown” which can never happen, but by multiple level shear layers near the solid wall surface. Therefore, these vortex packages have certain structure and are pretty stable with the energy transport channel to bring the energy down from the high energy inviscid area to the viscous boundary layer bottom. In this way, the vortex packages can be self-supported. The reason why the packages are sometime clear and sometime look like break or disappear is that the package is filled and surrounded by countless small vortices. Actually, these large vortex structures in the package are stable and must be kept in order to survive in a viscous flow. Of course, the structure of the package keeps changing inside and moving around. The packages can never stop and the relative motion between these packages can never stop either if the mean flow is not zero. This is the reason why the turbulent flow look likes “random”. The reason why turbulent flow consists of these packages is because only these packages can satisfy the Navier-Stokes equations. The mean flow with random perturbations will be rejected by Navier-Stokes equations. Apparently, these turbulence packages satisfy mass, momentum and energy conservation law and have the channel to supply enough energy for survival of the dissipative small vortices, but not the base flow like Blasius solution with random perturbations. In addition, we can find four vortices merge to two and two to one, but did not see one vortex break to two vortices and two break to four vortices. This may be restrained by the second thermodynamics law. 1. Sketch of turbulence structure Turbulence consists of many vortex packages (Figure1). Each vortex package has certain large vortex structure including vortex legs, multiple rings, secondary and tertiary vortices. The small vortex structure is generated by shear layers which are produced by sweeps and ejections due to large vortex rotation and consequent positive (high speed zone) and negative (low speed zone) spikes. These spikes will generate high shear layers and further multilevel vortex rings due to the shear layer instability (Figure 2.) Therefore, small vortices (turbulence) are not generated by “vortex breakdown” (impossible) but multiple level shear layer instability (Kelvin-Helmohotz type). Each vortex package has multiple level sweeps to bring the energy from high energy inviscid zone to the low level boundary layers to support those dissipative small vortices to survive (Figure 3.) These large and small vortex structures will further lose the symmetry and become disordered due to the internal instability of these multiple level vortex structure (Figure 4). Some people may argue that there is no accurate definition of vortex which could be vortex tube as most people think, blobs of vorticity, rotation centers or even vortex sheets (Davidson, 2004). However, small vortices (turbulence) can never be generated by ‘vortex breakdown” in any sense and the Richardson eddy cascade is not observed by any DNS or experiments. (1) Front view (2) Side view (3) Top view Figure 1 Turbulence consists of vortex packages Figure 2 Sketch of vortex package Figure 3 Energy brought down from inviscid zone to bottom through multiple level sweeps (a) Section view in y-z plane (b) Bottom view of positive spike Figure 4 The Flow lost symmetry in second level rings at t=15.0T 2. Late flow transition control Turbulence onset starts at the location of the first vortex ring formation. In order to delay the flow transition, we must delay the first ring formation. Whenever the first vortex ring is formed, turbulence generation is not avoidable. However, the small vortex generation is directly caused by strong sweeps which is generated by the first vortex ring (Figure 5). Changing the layout direction of large vortex rings could weaken the sweep and, therefore, to delay the small vortex formation. For example, an ejection of counter vortex may delay the first vortex ring formation and then delay the transition. The perfect circular shape and perpendicularly standing vortex rings would generate strongest sweeps and should be controlled (Figure 6.) Figure 5 Sweeps and ejections by vortex ring Figure 6 Perfectly circular shape and perpendicularly standing of the first vortex ring 3. Richardson vortex cascade revisit Figure 7 Sketch of Richardson’s cascade process (Frisch et al, 1978) Classical turbulence theory about vortex chains was given by Richardson (1924). He has a famous poem that “ big whirls have little whirls, which feed on their velocity; And little whirls have lesser whirls, and so on to viscosity in the molecular sense.” However, the vortex chain generated by large vortex breakdown is never observed. It is also hard to explain why one vortex breaks two and then four, etc. It is also hard to believe why viscosity plays role when the vortex size is equivalent to Re=1. How about eddy Re=2, 4, 6 etc. where viscosity does not play any role at all? As shown by our DNS, turbulence has different size of vortices from the large to the small. However, they are all generated by shear layer instability (K-H type) without exception and no vortex breakdown is observed. 4. Kolmogorov’s hypothesis revisit 4.1 Kolmogorov scale: The famous Kolmogorof scale is given by Russian Mathematician Kolmogorof in 1941. The scale is obtained by dimensional analysis. Assume the velocity and length related to the largest eddy are L and U , ν is the viscosity, e is the kinetic energy, the velocity and length related to the smallest eddy are V and η , we will have the energy relation:

In this paper, investigations on optimal topology and operation mode for low voltage GaN HEMT are performed. Analytical loss model of GaN HEMT, in which influences of circuit and package parasitics are accounted for, is developed as a tool to analyze losses in GaN HEMT in different switching conditions. Analysis results shows that when applied in both V out in and V out > 2V in situations in Boundary Conduction Mode with Valley Switching(BCM-VS) in a boost converter, where GaN HEMT is switched on when voltage across it is lowered, switching loss can be greatly reduced. Switching loss reduction results not only from the exemption of discharging the large output capacitance of GaN HEMT at high voltage, but also from the fact that parasitic inductance has much less effects on switching loss in GaN HEMT in BCM-VS than in Continuous Conduction Mode (CCM). Limitations and design tradeoffs when GaN HEMT is applied in BCM-VS are also revealed. Forward voltage of GaN HEMT in reverse conduction is high and its conduction should be prevented when V out > 2V in to achieve conduction loss reduction. This further loss reduction can be realized by switching on transistor before valley point. Besides, in BCM-VS, overvoltage on GaN HEMT is larger and oscillatory energy dissipation in circuit is higher than in CCM due to higher turn off current. Paralleling external capacitor to the transistor helps to ease voltage stress; however turn on loss will be increased. This loss increase is more severe in the case of V out in than V out > 2V in . Trade-offs on the selection of proper external capacitor value exists between increased switching loss and reduced voltage stress. Experimental setup is built to verify and demonstrate the analysis.

Some accidental processes in the operation of MMC flexible DC converter valve and the rapid switching of submodules will lead to the generation of some transient electromagnetic signals. This kind of transient signal is coupled to the IGBT drive circuit in the form of conduction disturbance through the parasitic parameters in the submodule loop, the gate voltage value of the IGBT drive port is further changed. This paper establishes the electromagnetic interference simulation model of a single submodule of 500 kV flexible DC converter valve, and analyzes the voltage change of IGBT driving port in the submodule under different matching strategies between converter valve and circuit breaker in short-circuit condition. The results show that under short-circuit conditions, positive and negative voltage spikes will be introduced at the IGBT drive port when the short-circuit fault is removed. When the device parameters in the sub-module are constant, the absolute value of the voltage spike is mainly determined by the driving circuit impedance and the common source inductance.

The design of gate drivers for SiC power MOSFETs needs to address various adverse effects induced by the parasitic inductance in the gate loop, such as false turn-on, gate overstress, and reduced switching speed. In this work, a single-polarity gate driver design featuring a low-voltage (LV) GaN HEMT for Miller clamping is presented. The lateral LV GaN HEMT can switch at a much higher speed than that of the SiC MOSFET, so that the proposed gate driver can well suppress false turn-on with a user-friendly OFF-state gate voltage of 0 V. Meanwhile, the reverse-conduction characteristics of the LV GaN HEMT allow the clamping of negative voltage spikes to protect the SiC MOSFET against gate overstress, which is shown to be detrimental to the gate reliability. In addition, the LV GaN HEMT can accelerate the turn-off process and suppress the gate-loop oscillation, thereby further reducing the switching loss, as verified by experiment results.

SiC mosfet has low on-state resistance and can work on high switching frequency, high voltage, and some other tough conditions with less temperature drift, which could provide the significant improvement of power density in power converters. However, for the bridge circuit in an actual converter, high dv/dt during fast switching transient of one mosfet will amplify the negative influence of parasitic components and produce the significant negative voltage spikes on the complementary mosfet , which will threaten its safe operation. This paper proposes a new gate driver circuit for SiC mosfet to attenuate the negative voltage spikes in a bridge circuit. The proposed gate driver adopts a simple voltage dividing circuit to generate a negative gate-source voltage as traditional and a passive triggered transistor with a series-connected capacitor to suppress the negative voltage spikes, which could satisfy the stringent requirements of fast switching SiC mosfet s under the high dc voltage condition with low cost and less complexity. An analysis is presented in this paper based on the simulation and experimental results with the performance comparison evaluated.

Silicon carbide (SiC) power modules have a wide range of applications due to their excellent electrical and thermal properties, such as high switching speed, low on-resistance, and high operating temperature. However, device reliability may suffer from overvoltage and current/voltage oscillation mainly caused by circuit parasitic inductance and capacitance. This phenomenon becomes more profound, especially at high-switching speed with high dv/dt and di/dt. It is therefore necessary to suppress the turn-off overvoltage and increase the damping ratio. This paper proposes a methodology to select the optimal resistance and capacitance values for the RC snubber circuit for SiC power modules. The methodology is verified through LTspice simulation. Based on the theoretical calculation and spice simulation, the optimal RC snubber capacitance and resistance are identified. In addition, results indicate that RC snubber capacitance can only suppress ringing, but not suppress surge voltage. The snubber resistance can mitigate the overvoltage.

Gallium nitride high electron mobility transistors (GaN HEMTs) have an advantage in high switching speed and high frequency applications. However, the protection circuit for GaN HEMTs requires a fast response time due to the low robustness of short-circuit condition of GaN HEMTs. In addition, the high switching speed of GaN HEMTs generates severe noise, which causes a false-triggering for the protection circuit. This article is focused on analyzing the effect of switching noise on the protection circuit and proposes the protection circuit for GaN HEMTs with fast response speed and strong noise immunity. The protection circuit has been verified by SPICE simulation. The simulation results show that the protection delay of protection circuit is within 101 ns with strong noise immunity at normal operation.

Wide-bandgap devices, such as silicon carbide and gallium nitride, have high switching speed potential. However, the actual speed in practical application is limited by circuit parasitics and interaction between high-side switch and lowside switch in a phase-leg configuration, known as crosstalk effect. This article proposes an isolated voltage source gate driver with crosstalk suppression capability to take full advantage of the inherent high switching speed ability of silicon-carbide devices. By applying variable gate voltage through the auxiliary circuit, the crosstalk problem can be mitigated. Using the original gate-source voltage as auxiliary circuit driving signal, the gate driver does not introduce any extra control signals, which avoids additional signal/power isolations and makes the auxiliary circuit very convenient to be implemented on the existing commercial gate driver. The auxiliary circuit makes the gate voltage rise from 0 V other than -5 V when the switch turns on, leading to faster switching speed and lower switching loss compared with a traditional gate driver. LTSPICE simulation and double pulse test experiment based on 1.2-kV/60-A silicon-carbide MOSFETs are conducted to evaluate the crosstalk suppression capability of the proposed gate driver.

This paper proposes a low cost gate driver of Silicon Carbide (SiC) MOSFET with a passive triggered auxiliary transistor in a phase-leg configuration. Silicon Carbide MOSFET can work on high blocking voltage and high switching frequency with less temperature drift. However, high switching speed may amplify the negative influence of parasitic components and produce significant voltage spikes during switching transient. Therefore, eliminating the spikes of gate-source voltage in a phase-leg configuration plays an important role in providing the safe driving and low switching losses. The proposed gate driver uses a simple voltage dividing circuit to generate a negative gate-source voltage and a passive triggered transistor with a series capacitor to suppress negative voltage spikes, which could satisfy the stringent requirements of high switching SiC MOSFETs with low cost and less complexity. The performance of proposed gate driver is evaluated by simulation and experimental results.

Gallium nitride high electron mobility transistors (GaN HEMTs) show significant advantages in high frequency and high switching speed applications, which has gathered great interests. Due to the low short-circuit withstand capacity, the short-circuit protection with high response speed is critical for GaN HEMTs. Besides, the high switching speed of GaN HEMTs brings severe interference to protection circuits, which becomes a key obstacle for ultrafast short-circuit protection. This article analyzes the interference mechanism of dv/dt noise on the desaturation short-circuit protection circuits in detail. According to the noise propagation model, an improved protection circuit is proposed, in which a discharging capacitor is employed to enhance the noise immunity behavior. In addition, optimization methods of the key parameters are presented, which allow the designers to evaluate the noise immunity of the protection circuits with different parameters during the design processes. The experimental results show that the response time of the protection circuit is within 110 ns. Without the proposed methods, the noise introduced by a low dv/dt of 2.5 V/ns will generate false-trigger protection actions. The improved protection circuit can survive under the dv/dt up to 84 V/ns, which verifies the validity of the proposed optimization methods.