Abstract

The impact of compressive and tensile stress on CMOS performance is studied for <;100>; and <;110>; oriented silicon and SiGe channels. The <;110>; channel direction is found to be more stress sensitive whereas the <;100>; oriented transistor has a higher initial hole mobility. These results recommend to use the <;110>; channel orientation for high performance application due to the high drive current gain and <;100>; channel orientation for low power applications where no stress elements are included to ease the overall process complexity and to decrease costs.

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