Miller Compensation: Optimal Design for Operational Amplifiers with a Required Settling Time

Abstract

Optimizing the settling response of an operational amplifier can be a serious design issue in today's low-power CMOS technologies. Several design challenges emerge when improving the linear and nonlinear responses of an amplifier. In this paper, we developed a settling model for use in design and optimization of two-stage Miller-compensated amplifiers. Using this model, the closed-form relations between settling time/settling error, gain-bandwidth product, noise, power and stability have been obtained. These relations are employed to form a settling-based design routine for Miller-compensated amplifiers. Simulation results in 0.18- $$\upmu $$ μ m CMOS validate the effectiveness of the proposed routine. In a design prototype, it predicts the settling time with an error less than 3 %. In another design example, the relationship between settling time and gain-bandwidth has been evaluated with an accuracy higher than 95 %. The proposed design routine is used to implement a 40 MS/s sample-and-hold amplifier. It achieves a settling time and signal-to-noise-plus-distortion ratio equal to 12.5 ns and 82 dB, respectively.