Microstructure control of (Pb,Sr)TiO 3 films on Pt/Ti/SiO 2/Si substrates by a TiO 2 buffer layer

Abstract

A thin TiO 2 buffer layer was used to control the microstructure and electrical properties of the polycrystalline (Pb,Sr)TiO 3 (PST) films produced by a Sol–Gel method on Pt(111)/Ti/SiO 2/Si(100) substrates. The PST films included (Pb 0.6Sr 0.4)TiO 3 (PST40) and (Pb 0.4Sr 0.6)TiO 3 (PST60). It was found that a crystallized TiO 2 buffer layer with a thickness of nearly 5 nm was critical for improving the crystallinity and surface morphology of both the thinner (about 40 nm) and thicker (about 330 nm) PST films, which exhibited a (l00) preferred orientation and much smoother surface comparing with those without the buffer layer. The electrical properties of the PST films having TiO 2 buffer layer were also improved. For 330-nm-thick PST40 films, the dielectric constant and its tunability by dc voltage were increased from 482 and 26.8% at 10 kHz to 590 and 51.2%, while the loss and leakage current density were reduced from 0.04 and 4.26 × 10 −4 A/cm 2 at 100 kV/cm to 0.034 and 7.63 × 10 −6 A/cm 2, respectively. Similar results were also found in the PST60 films.