Micro/nano functional structure manufacturing from difficult-to-cut materials by etching and its combined machining strategies: A review

In this paper, an isotropic dry plasma etching was used to release the suspended SiO2 microcantilever from the substrate of SOI wafer. Employing the plasma dry etching technique, the frontside etching for the SiO2 microcantilever release is done using the Oxford Plasmalab System 100. To obtain the optimum condition for the microcantilever release using the plasma etcher, the etching parameters involved are 100 sccm of SF6 flow, 2000 W of capacitively coupled plasma (CCP) power, 3 W of inductively coupled plasma (ICP) power, 20°C of etching temperature and 30 mTorr chamber pressure. The optimum parameters yield lateral etch rate of about 5 μm/min and vertical etch rate of about 8 μm/min. Two etching methods have been considered in this study. The first method employs only the isotropic etching to realize the microcantilever release while the second method utilizes both the anisotropic etching and the isotropic etching. For the second method, the process starts with the anisotropic etching from the deep reactive ion etching (DRIE) system which is then followed by the isotropic etching to complete the microcantilever releasing process. The purpose of the anisotropic etching is to create an etching window for the subsequent isotropic etching process. By using double-step etching method which combines both isotropic and anisotropic plasma etching for the microcantilever release process, the releasing process of suspended microcantilever is significantly improved.

1. Introduction Ge has been received much attention as the next generation semiconductor materials due to its attractive characteristics such as high carrier mobility[1] and narrow bandgap corresponding near infrared wavelength[2]. In order to utilize its characteristics for the applications, Ge-on-Insulator (GOI) structure is necessary. Several fabrication methods for GOI have been suggested such as wafer bonding and mechanical thinning[3], Smart-CutTM[4,5], and SiGe condensation[6]. It is well known Smart-CutTM is widely used for commercial Si-on-Insulator (SOI) fabrication. However, Ge is more sensitive to damages caused by ion implantation and difficult to recover damages completely. Therefore, the best way for GOI fabrication have not been developed.In early stage of SOI R&D, many approaches were proposed, too[7]. Wafer bonding and etchback is one of the simplest technique, and the advantage of this method is any damages due to ion implantation or mechanical stress are not induced to the top semiconductor layer. Therefore, we focused on etchback technique for GOI fabrication. It is necessary to develop appropriate Ge etching method with moderate etching rate and keeping or improving surface flatness. In this study, we aim to develop appropriate etching method of Ge for etchback GOI fabrication. 2. Experimental and results We used single side mirror polished Ge wafer with a thickness of 500 μm. Figure 1 shows the experimental procedure in this study. The original polished top surface was covered by photoresist to avoid etching from this side. Firstly, we confirmed HF + HNO3 mixture solution for Ge etching because it is widely known as etching solution for Si. Figure 2 shows optical microscope images for the back side (non-polished side) of (100)-oriented Ge wafer (a) before etching and (b) after etching by HF + HNO3 for 7 minutes. By etching, surface uniformity drastically improved. So, wet etching can be used for Ge thinning and planarization. However, this solution reacts handle Si substrate of GOI, too. As an alternative etching solution, we selected HF + H2O2 mixture[8]. Figure 3 shows the etching result of (100)-oriented Ge etched by HF + H2O2 + H2O (7:7:6) solution. Although Ge was etched similar to Fig. 2(b), surface uniformity was inferior to HF + HNO3 etching. To improve surface uniformity, CH3COOH was added as diluent instead of H2O because politic amount of CH3COOH into HF + HNO3 solution leads isotropic etching and mirror plane on Si surface[9]. Figures 4 shows the etching results of (100)-oriented Ge by HF + H2O2 + CH3COOH (1:1:1) solution. Surface uniformity improved than Fig. 3 and there is no orientation dependence (data not shown). Therefore, isotropic etching occurs on Ge surface. The average etching rate in the first 20 minutes calculated from the lost masses was 7.9 μm/min. It should be noted any agitation was not carried out during etching and longer etching time leads decreasing of etching rate. Possible etching reaction is expressed as[10]:2CH3COOH + 2H2O2 → 2CH3COOOH + 2H2O (1)Ge + 2CH3COOOH + 2e - → Ge2+ + 2CH3COO- + 2OH- (2)As further investigation of surface uniformity, atomic force microscope (AFM) observation was carried out. Figure 5 shows AFM images for backside of (100)-oriented Ge etched for 110 minutes. The RMS of 30×30 μm2 area is 0.48 nm. Compared with the RMS of original backside (> 5 μm), the surface flatness is improved drastically. In the conference, electrical characteristics of etched surface will be presented. 3. Conclusions For etchback GOI fabrication, we study isotropic etching for Ge. HF + H2O2 + CH3COOH mixture solution can etch Ge isotropic and improving surface uniformity. This solution has a potential as etching solution for etchback to make GOI structure. Acknowledgements This work was supported by JSPS KAKENHI Grant Numbers 19K15028 and 19H05616. Appendix Original concentrations of the chemicals in this study are HF: 49 wt%, HNO3: 69 wt%, H2O2: 30 wt%, and CH3COOH: 99.7 wt%. All compounding ratios in this article are volume rate.

As semiconductor devices are miniaturized to sub-10 nm dimensions, introducing new device structures, integration schemes, and materials brings many challenges to the high-volume manufacturing of these devices. A new structure with gate-all-around (GAA) nanosheets has been introduced to reduce the power consumption of transistors and achieve higher transistor integration density. A complementary field-effect transistor (CFET) is also investigated as a next-generation logic device. For advanced semiconductor memory devices, 3D NAND flash has been introduced to achieve higher bit densities, and 3D DRAM is expected to be introduced in the future. Fabricating these three-dimensional (3D) devices requires isotropic etching of thin films with atomic layer control, high selectivity to underlying materials, and high uniformity from top to bottom of high-aspect-ratio 3D structures. Atomic layer etching (ALE) is a promising method to meet these demands and it can be divided into two major categories, directional (anisotropic) and nondirectional (isotropic) etching, with many subdivisions of both categories. Isotropic ALE is often referred to as thermal ALE because it utilizes the random motion of gas molecules and thermal energy for surface reactions. Thermal ALE is a promising method for isotropic etching with atomic-level precision and high conformality over 3D structures. One method to implement thermal ALE is to create a surface-modified layer through reactive radicals or gas exposures and to desorb it by temperature modulation of the surface of thin films. We developed a dry chemical removal (DCR) tool with an infrared (IR) wafer annealing and quick cooling system to perform highly selective thermal ALE for various materials. Thermal ALE was demonstrated for Si3N4 and SiO2 films using the formation and desorption of (NH4)2SiF6-based surface-modified layers. The surface-modified layer was formed on the films using exposure to radicals generated in hydrofluorocarbon-based plasmas or subsequent gas exposures to HF and NH3. The surface-modified layer can be desorbed by IR annealing. After the annealing, the substrate is cooled down to the original temperature and the ALE cycle can be repeated to obtain a target etching amount. Thermal ALE processes for W and TiN films were also demonstrated by the formation and desorption of halogenated surface-modified layers. These ALE processes show a self-limiting formation of modified layers, enabling conformal and precisely controlled etching. In addition to these ALE processes, spontaneous and highly selective etching of SiO2 was demonstrated on the DCR tools using HF/CH3OH vapor. SiO2 films can be etched spontaneously with high selectivity to SiN films when the temperature of the substrate is lower than −20ºC.

We present 3-D modeling results on resist line-edge-roughness (LER) transfer to underlying films during plasma etching. After generating random fractal resist sidewalls with controlled roughness parameters, we model and contrast the nanoscale roughness phenomena for both resist and underlayer sidewalls in a two-layer stack using two different plasma processes in three scenarios: (1) pattern transfer; (2) resist trimming; and (3) resist trimming followed by pattern transfer. In the pattern transfer process, etching is considered ion driven and anisotropic. The protrusions of the rough, trimmed or nontrimmed, resist sidewall act as a shadowing mask for the incident ions. It is found that shadowing of ions is enough to induce the, well known by experiments, striations at the sidewalls of both the underlayer and the resist. Pattern transfer induces a decrease of rms roughness but has no important effects on the correlation length. In the trimming process, the evolution of the resist sidewall is modeled with an isotropic etching process not affecting the underlayer. The trimming process causes a decrease of the rms value of the resist sidewall and an increase of its correlation length and roughness exponent. For sufficiently long trimming times, the change of LER parameters becomes less intense. In the case of trimming followed by pattern transfer, the striations of the underlayer widen with trimming time, and pattern transfer further reduces all LER parameters. The effect of trimming on the rms roughness of the underlayer is important in the case of initially anisotropic resist sidewall. For both trimming and pattern transfer, a stronger relative reduction on rms roughness of both the resist and the underlayer sidewalls is obtained for smaller correlation length and larger rms roughness of the initial resist.

This paper reports a new design and microfabrication process for high sensing guard-armed silicon dioxide (SiO2 ) microcantilever sensor, which can be widely used in chemical, environmental and biomedical applications. One sensor platform consists of two SiO2 cantilever beams as the sensing and reference elements, two connecting wings, and three guard arms. The guard arms prevent damage to the cantilever beam from collision. To efficiently release the SiO2 cantilevers from the silicon substrate, an isotropic etch method using inductively coupled plasma (ICP) was developed. The isotropic etching with ICP system provides an advantage in good profile control and high etching rate than wet isotropic etching or conventional RIE (reactive ion etching); however, it has not been gained many attentions. In this work, the effects of chamber pressure, plasma source power, substrate power, SF6 flow rate relating with Si etching rate, undercutting rate, and isotropic ratio were investigated and discussed. The optimum isotropic etching process achieved a 9.1 mum/min etch rate, 70% isotropic ratio, and 92% etching uniformity. The SiO2 cantilever sensor was fabricated and the cantilever beam was successfully released using a patterned photoresist layer as an etching mask. This plasma isotropic etching release processing can be also applied to release other SiO2 or metal suspended MEMS structures, such as bridges and membranes, with a fast etch rate and reasonable isotropic ratio.

Isotropic etching is traditionally performed using liquid-based wet etching techniques. However, with the increasing integration of devices, achieving conformal etching in high aspect ratio patterns becomes difficult, as liquid chemicals are limited in their ability to penetrate deep into these structures. Moreover, during the drying phase following chemical treatment, surface tension can lead to pattern collapse. Consequently, there is a growing need for dry isotropic etching methods to replace conventional wet etching in advanced device manufacturing.In cases where high selectivity for SiO2 isotropic dry etching is required, mixtures of fluorine-based and hydrogen-based gases are typically used to generate HF, which acts as the etchant for SiO2. SiO2 can be etched through two main mechanisms. The first mechanism involves the direct reaction of HF with H2O or alcohol to etch SiO2. The second mechanism involves the formation of (NH4)2SiF6 salt through the reaction of HF with NH3, which occurs in a plasma containing NH3 and NF3. This (NH4)2SiF6 salt is then sublimated and removed in a subsequent heating process at temperatures above 100°C.The reaction of HF with NH3 to form (NH4)2SiF6 can lead to the generation of ammonium salts that may act as contaminants within the etching chamber. Additionally, this approach necessitates an extra thermal treatment step to eliminate the (NH4)2SiF6 salt. HF can be supplied either directly as vapor or generated through plasma containing fluorine and hydrogen. Plasma-based methods generally offer advantages in terms of safety and process efficiency compared to direct HF vapor usageIn this study, we investigated an isotropic dry etching process in which HF etchant is generated by discharging fluorine-based and hydrogen-based gas mixtures. A vapor-phase solvent is supplied outside the discharge region to ionize HF and directly etch SiO2. When using H2O vapor as the solvent, we achieved the etch selectivity of SiO2 over SiNx and poly Si higher than 100 and 600, respectively, was obtained while having SiO2 EPC of ~30 nm/min by optimized conditions. The etching mechanism was clarified through gas-phase and surface analyses using optical emission spectroscopy (OES), quadrupole mass spectrometry (QMS), and X-ray photoelectron spectroscopy (XPS). To assess pattern collapse, we compared the wet phase and vapor phase processes applied to the Si trench pattern. The results suggest that using fluorine and hydrogen-based remote plasmas with a vapor-phase solvent is promising for highly selective isotropic SiO2 etching in the fabrication of next-generation 3D devices.

The ability to achieve near-atomic precision in etching different materials when transferring lithographically defined templates is a requirement of increasing importance for nanoscale structure fabrication in the semiconductor and related industries. The use of ultra-thin gate dielectrics, ultra thin channels, and sub-20 nm film thicknesses in field effect transistors and other devices requires near-atomic scale etching control and selectivity. There is an emerging consensus that as critical dimensions approach the sub-10 nm scale, the need for an etching method corresponding to Atomic Layer Deposition (ALD), i.e. Atomic Layer Etching (ALE), has become essential, and that the more than 30-year quest to complement/replace continuous directional plasma etching (PE) methods for critical applications by a sequence of individual, self-limited surface reaction steps has reached a crucial stage. A key advantage of this approach relative to continuous PE is that it enables optimization of the individual steps with regard to reactant adsorption, self-limited etching, selectivity relative to other materials, and damage of critical surface layers. In this overview we present basic approaches to ALE of materials, discuss similarities/crucial differences relative to thermal and plasma-enhanced ALD, and then review selected results on ALE of materials aimed at pattern transfer. The overview concludes with a discussion of opportunities and challenges ahead.

Laser surface texturing (LST) employs high‐energy laser radiation to promote controlled material ablation, enabling the creation of surface features that can significantly enhance material performance. Applications range from friction reduction to improved biological interactions, demonstrating the versatility of LST. While the technique is well established for metals and alloys, its application to ceramics still faces considerable challenges that hinder broader adoption. This review aims to provide a comprehensive overview of LST applied to ceramics, focusing on laser‐ceramic interactions and the key processing parameters that influence surface structuring. Representative examples of functional ceramic surfaces produced via LST are discussed, along with their performance in various domains, including optical, thermal, electronic, electrochemical, biomedical, and tribological applications. This review showcases the huge potential of LST for innovation in ceramics, envisioning future perspectives on the role of LST in ceramic surface engineering.

Understanding the self-limiting effect in picosecond laser single and multiple parallel pass drilling/machining of CFRP composite and mild steel

The threshold voltage properties of NMOS structure was affected by varying the etching rate using Silvaco TCAD tools software. The effect of etching rate in the etching process of NMOS structure was investigated with different etching methods. The etching methods which are isotropic wet etching and isotropic RIE etching have reduced the length of polysilicon gate and decreased the threshold voltage by increasing the etching rate. The directional RIE etching method gives close pattern of gate to the photoresist pattern and increased the threshold voltage properties gradually by increasing the etching rate.

Directed self-assembly (DSA) of block copolymers (BCPs) is one of the most promising patterning technologies for future lithography nodes. However, one of the biggest challenges to DSA is the pattern transfer by plasma etching from BCP to hardmask (HM) because the etch selectivity between BCP and neutral brush layer underneath is usually not high enough to enable robust pattern transfer. This paper will explore the plasma etch conditions of both BCPs and neutral brush layers that may improve selectivity and allow a more robust pattern transfer of DSA patterns into the hardmask layer. The plasma etching parameters that are under investigation include the selection of oxidative or reductive etch chemistries, as well as plasma gas pressure, power, and gas mixture fractions. Investigation into the relationship between BCP/neutral brush layer materials with varying chemical compositions and the plasma etching conditions will be highlighted. The culmination of this work will demonstrate important etch parameters that allow BCPs and neutral brush layers to be etched into the underlying hardmask layer with a large process window.

Microelectronic device fabrication has traditionally been performed by selective removal or etching of material from deposited films to create patterns. Plasma etching has been the mainstay of this process since the early 1970s. The introduction of copper (Cu) metallization (~1997) by IBM resulted in the development of additive approaches (e.g., damascene process) due to the inability to plasma etch Cu. Despite attempts to plasma etch Cu as early as 1980, the only viable plasma-based methods in this time frame were inert gas sputtering, where selectivity to underlying layers and low etch rate were problematic, or chlorinated vapors that required elevated temperatures (>200 C) or significant ion bombardment energies to volatilize Cu chlorides. Both approaches required a hard mask rather than photoresist layers to ensure mask stability and precise pattern transfer. Due to the inability to form high volatility Cu halides that could be removed readily by plasma processes, other non-plasma or partial plasma approaches to Cu etching at lower temperatures were investigated. Addition of a UV lamp to facilitate excitation and desorption of volatile Cu chlorides in plasma etching was invoked. Formation and volatilization of copper by oxidation followed by complexation with organic ligands at lower (~150 C) temperatures was first reported in the mid-1990s, but this processes generated isotropic etch patterns; more recent approaches have reported anisotropy. Plasma chlorination followed by a liquid etch to remove the chlorinated Cu was also reported; due to the directionality of the plasma chlorination step, anisotropic profiles resulted. Hydrogen-based etching of Cu films was reported in 2010, initially with a two-step process consisting of plasma chlorination followed by a hydrogen plasma step to remove volatile products. This effort subsequently demonstrated that etching by pure hydrogen in a one-step process was possible albeit with low etch rates; etch rate increases were observed with vapor additives. Pure hydrogen plasmas etched photoresist layers, thereby requiring hard masks, but additives allowed employment of photoresist as a mask layer. Anisotropic etch profiles from these hydrogen-based processes were possible, in part due to additives protecting sidewalls and photoresist from etching and to ion bombardment during etching.This presentation will describe the development of Cu etching and patterning methods beginning in the 1970s. Mechanistic considerations of the various processes reported will be discussed and the current needs and limitations of these approaches indicated.

As integrated circuit feature sizes have continued to decrease, plasma etching has become the method of choice for achieving the resolution and process control required for device fabrication. To maintain tight control, the precise detection of etch endpoint is very important. A variety of endpoint detection schemes are available. These include the optical emission spectroscopy, mass spectroscopy, monitoring of chamber pressure and dc bias, and laser interferometry. This paper deals with the application of laser inteferometry for endpoint detection in plasma or dry etching, which is the removal of a film in a plasma or low pressure gaseous discharge. Etching consists of the following steps. The exposed film, i.e. not covered by resist, is removed by chemical and/or physical processes which are determined by the type of etch. In plasma etching, the etching is done by ions and highly reactive chemical species called free radicals. There are many different types of dry etch methods. In this case, the process was RIE, reactive ion etching, where chemical and physical effects interact to produce the etch.

Plasma etching is a powerful technique for transferring high-resolution lithographic patterns into HgCdTe material with low etch-induced damage, and it is important for fabricating small-pixel-size HgCdTe infrared focal plane array (IRFPA) detectors. P- to n-type conversion is known to occur during plasma etching of vacancy-doped HgCdTe; however, it is usually unwanted and its removal requires extra steps. Etching at cryogenic temperatures can reduce the etch-induced type conversion depth in HgCdTe via the electrical damage mechanism. Laser beam-induced current (LBIC) is a nondestructive photoelectric characterization technique which can provide information regarding the vertical and lateral electrical field distribution, such as defects and p–n junctions. In this work, inductively coupled plasma (ICP) etching of HgCdTe was implemented at cryogenic temperatures. For an Ar/CH4 (30:1 in SCCM) plasma with ICP input power of 1000 W and RF-coupled DC bias of ∼ 25 V, a HgCdTe sample was dry-etched at 123 K for 5 min using ICP. The sample was then processed to remove a thin layer of the plasma-etched region while maintaining a ladder-like damaged layer by continuously controlling the wet chemical etching time. Combining the ladder etching method and LBIC measurement, the ICP etching-induced electrical damage depth was measured and estimated to be about 20 nm. The results indicate that ICP etching at cryogenic temperatures can significantly suppress plasma etching-induced electrical damage, which is beneficial for defining HgCdTe mesa arrays.

As grown, CVD diamond windows have low infra-red absorption, but are highly scattering in transmission due to the presence of crystalline facets on the material surface. Conventionally, these facets are removed by mechanical polishing techniques which are slow, not easily adapted to complex shapes, and which can lead to mechanical damage and loss of strength. In this work, an attempt has been made to use a patented plasma etching and deposition method to polish CVD diamond window material optically flat. Low pressure radio frequency (rf) discharges of a variety of plasma etchant gases (Ar, H<SUB>2</SUB> CCl<SUB>4</SUB>, SF<SUB>6</SUB>, CO<SUB>2</SUB>) have been used to etch the diamond surface. Etch rates of 2000 angstroms/minute can be obtained using carefully optimized etch chemistries. It has been shown that plasma etching the diamond window under conditions which give a high self-induced dc bias causes preferential sputtering of the edges of microcrystallites and hence polishes the diamond surface flat. Certain plasma chemistries, notably those involving chlorine, have also been found to flatten the surface by preferentially removing the crystalline facets. By plasma depositing silicon oxide on the window material it is possible to planarize the surface prior to a plasma etch stage and then plasma etch away the silicon oxide and diamond in a subsequent etch stage so smoothing the diamond surface. The affect of these polishing methods on a variety of CVD diamond films is discussed and the limitations of the technique addressed.