Methodology and backend flow optimization for 3D

Abstract

The article deals with the complexity of the workflow used when integrated circuits are implemented using 2D electronic design automation (EDA) tools and adapting the workflow for 3D integrated circuits. If some issues are not identified promptly in the workflow, the working time to produce an integrated circuit is increased. By analyzing and refining workflow, identifying bottlenecks and early problems in a design, the optimization process will ensure an error-minimized trajectory from synthesis to final design prepared for manufacturing. Considering all the details at every stage of the working flow will help the backend designer to solve problems faster and save time. It was created detailed scripts for automatization of the process at every stage including floorplan, power plan, placement, clock tree synthesis, routing and all physical and logical analysis. The workflow was optimized using loops at all levels, extracting important information at every level and improving the process of working. Moreover, optimization techniques contribute significantly to precision and quality in design implementation. This working flow can be used to implement 3D integrated circuits with automated 2D tools from Synopsis.