Abstract
As digital system clock rates increase, the susceptibility to failure in synchronizing asynchronous inputs increases. Because of this phenomena, the need for flip flops in high speed technologies that can resist becoming metastable and recover quickly has also increased. SONET and ATM are typical applications where there are concerns regarding metastability. This paper presents the results of characterizing a high speed GaAs digital logic family, SCFL (Source Coupled FET Logic) for metastability and the efforts to improve the metastability characteristics of the flip flops. An architecture which shows a significant reduction in failure rate was designed, simulated, fabricated, and characterized.
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