Abstract
The metastability of catch-detect DFFs in Vernier time-to-digital converters (TDCs) causes the DFFs to yield an erroneous, reducing the resolution of the TDCs. In this paper we propose a new metastability correction technique for true single-phase clock (TSPC) D flip flops (DFFs) in catch detection of Vernier TDCs. The proposed technique eliminates the metastability-induced errors of catch-detect DFFs in Vernier TDCs without affecting both resolution and conversion time. The effectiveness of the techniques is validated using the simulation results of two 8-stage Vernier TDC designed in a TMSC 130 nm CMOS technology.
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