Memristor based Majority Logic Adders for Error Resilient Image Processing Applications

Approximate computing is an emerging paradigm to make a trade-off between accuracy and hardware parameters in error resilient applications. Multiplication is one of the main operators in various digital signal processing (DSP) applications. In this paper, we propose two novel approximate 4:2 compressors based on carbon nanotube field-effect transistors (CNFETs). To evaluate the proposed designs, comprehensive simulations are carried out at both transistor and application levels. At the transistor level, all circuits are evaluated using the HSPICE simulator tool. Simulation results demonstrate remarkable improvements in terms of power consumption, delay, power-delay product (PDP), and transistor count in comparison to the previous approximate compressors. For instance, the proposed 12TAC design improves the PDP at least 33% and at most 84% compared to its counterparts at 0.65 V power supply. At the application level, we apply all designs in image multiplication by using MATLAB, and the important image quality metrics are evaluated. Finally, we use some figures of merit (FOM) that include both hardware and accuracy metrics to study the efficacy of cells. The results indicate that the proposed circuits have a better compromise between hardware and accuracy metrics.

Adders are constituted as the fundamental blocks of arithmetic circuits and are considered important for computation devices. Approximate computing has become a popular and developing area, promising to provide energy-efficient circuits with low power and high performance. In this paper, 10T approximate adder (AA) and 13T approximate adder (AA) designs using carbon nanotube field-effect transistor (CNFET) technology are presented. The simulation for the proposed 10T approximate adder and 13T approximate adder designs were carried out using the HSPICE tool with 32 nm CNFET technology. The metrics, such as average power, power-delay product (PDP), energy delay product (EDP) and propagation delay, were carried out through the HSPICE tool and compared to the existing circuit designs. The supply voltage Vdd provided for the proposed circuit designs was 0.9 V. The results indicated that among the existing full adders and approximate adders found in the review of adders, the proposed circuits consumed less PDP and minimum power with more accuracy.

Approximate computing is a new way of performing calculations in digital systems. By applying this method, performance metrics, e.g., speed, are improved, but in return for this, the accuracy of the calculations is reduced. Memristors are electrical elements that can be used to perform logical calculations along with data storage. This makes memristors a good choice for In-Memory Computation (IMC). IMPLY logic is the first stateful logic proposed for memristive IMC. Approximate computing in memory, particularly using memristive stateful logic, has not been explored yet. In this paper, we combine these two concepts and propose a novel algorithm for serial IMPLY-based adders to implement an approximate full-adder. The proposed approximate full-adder was assessed in an image processing application, and image quality metrics like Peak Signal to Noise Ratio (PSNR) were calculated. In addition, different error quality metrics like Error Distance (ED) and Mean ED (MED) were assessed. Our study shows that the proposed method can achieve up to 40% improvement whereas maintaining the introduced error in an acceptable range (i.e., a PSNR above 32.4).

The limitations of Complementary Metal Oxide Semiconductor (CMOS) such as high-power dissipation, short channel effects, and high lithography has prompted scientists to look forward to alternatives. Many nanotechnologies were emerged and still in the competition such as Fin Field-Effect Transistor (FinFET), Carbon Nanotube Field-Effect Transistor (CNFET), Quantum-dot Cellular Automata (QCA). QCA is a new nanoelectronics technology used a new method for calculations and it is a promising technology in terms of power dissipation. In QCA, circuit complexity is depending on cell count, area and latency. For commercial purposes a universal gate is necessary, this gate can be used alone to design any Boolean function, where in CMOS technology, the NAND or NOT gates have the ability to be a universal gate. The dominant gates in QCA are the majority gate with inverter where QCA circuits cannot be designed using only a universal gate. Because the structure of the gate is important in QCA, this paper introduces a new low complexity singular block that can be used as a universal block. The proposed block can be used to form AND, OR, NOT, Exclusive-OR (XOR) and Multiplexer (MUX). So, this block not just used to design any circuit but also it can be used to form other important functions XOR and MUX to build large circuits in an optimum form.

Multiplication scheme is one of the most essential factors, which is time consuming. Designers and manufacturers of processors emphasis on methods which would not only perform the multiplication scheme in a rapid manner, but would reduce the physical aspect of the design as well; hence, a reduction in power consumption. Addition is one of the fundamental factors in multiplication. Pre-designing of circuits and transistors’ levels used to be made through Metal Oxide Semiconductor Field Effect Transistor (MOSFET), but now, due to scaling and difficulties thereof, new technologies like Single Electron Transistor (SET), Quantum-dot Cellular Automata (QCA) and Carbon Nanotube Field Effect Transistor (CNFET) are introduced. Among the new technologies, CNFET has become center of attention due to similarities in electronic features in relation to MOSFET. A comparison made between CNFET with MOSFET technologies indicate that, power delay product (PDP) and power leakage can be less in nanotube transistors. Field effect transistor circuit’s simulations are accomplished through HSPICE simulator. The simulation results indicate that this proposed Three-operand Carbon Nanotube Multiplier has a better performance in comparison with the threeoperand multiplication done on computers nowadays, which we call it classical multiplier in this article.

Prior research studies have shown that the peak signal to noise ratio (PSNR) is the most frequent watermarked image quality metric that is used for determining the levels of strength and weakness of watermarking algorithms. Conversely, normalised cross correlation (NCC) is the most common metric used after attacks were applied to a watermarked image to verify the strength of the algorithm used. Many researchers have used these approaches to evaluate their algorithms. These strategies have been used for a long time, however, which unfortunately limits the value of PSNR and NCC in reflecting the strength and weakness of the watermarking algorithms. This paper considers this issue to determine the threshold values of these two parameters in reflecting the amount of strength and weakness of the watermarking algorithms. We used our novel watermarking technique for embedding four watermarks in intermediate significant bits (ISB) of six image files one-by-one through replacing the image pixels with new pixels and, at the same time, keeping the new pixels very close to the original pixels. This approach gains an improved robustness based on the PSNR and NCC values that were gathered. A neural network model was built that uses the image quality metrics (PSNR and NCC) values obtained from the watermarking of six grey-scale images that use ISB as the desired output and that are trained for each watermarked image’s PSNR and NCC. The neural network predicts the watermarked image’s PSNR together with NCC after the attacks when a portion of the output of the same or different types of image quality metrics (PSNR and NCC) are obtained. The results indicate that the NCC metric fluctuates before the PSNR values deteriorate.

Peak signal to noise ratio (PSNR), the de facto universal image quality metric has been widely criticized as having poor correlation with human subjective quality ratings. In this paper, it will be illustrated that the low performance of PSNR as an image quality metric is partially due to its inability of differentiating image contents. And it is revealed that the deviation between subjective score and PSNR for each type of distortions can be systematically captured by perceptual complexity of the target image. The free energy modelling technique is then introduced to simulate the human cognitive process and measure perceptual complexity of an image. Then it is shown that performance of PSNR can be effectively improved using a linear score mapping process considering image free energy and distortion type. The proposed free energy adjusted peak signal to noise ratio (FEA-PSNR) does not change computational steps the of ordinary PSNR and therefore it inherits the merits of being simple, derivable and physically meaningful. So FEA-PSNR can be easily integrated into existing PSNR based image processing systems to achieve more visually plausible results. And the proposed analysis approach can be extended to other types of image quality metrics for enhanced performance.

When a mobile phone camera is tested and benchmarked, the significance of image quality metrics is widely acknowledged. There are also existing methods to evaluate the camera speed. However, the speed or rapidity metrics of the mobile phone’s camera system has not been used with the quality metrics even if the camera speed has become a more and more important camera performance feature. There are several tasks in this work. First, the most important image quality and speed-related metrics of a mobile phone’s camera system are collected from the standards and papers and, also, novel speed metrics are identified. Second, combinations of the quality and speed metrics are validated using mobile phones on the market. The measurements are done toward application programming interface of different operating systems. Finally, the results are evaluated and conclusions are made. The paper defines a solution to combine different image quality and speed metrics to a single benchmarking score. A proposal of the combined benchmarking metric is evaluated using measurements of 25 mobile phone cameras on the market. The paper is a continuation of a previous benchmarking work expanded with visual noise measurement and updates of the latest mobile phone versions.

Image processing with high-speed and low-energy approximate arithmetic circuit

Approximate computing aims to reduce the power consumption and design complexity of digital systems with the cost of a tolerable error. In this article, two ultra-efficient magnetic approximate full adders are presented for computing-in-memory applications. The proposed ultra-efficient full adder blocks are coupled with a memory cell based on magnetic tunnel junction (MTJ) to allow for nonvolatility. Therefore, they can be power-gated when required. Both the proposed full adders have simple designs and are energy-efficient. Instead of introducing dedicated write-driver and read circuits, the restorer latch inverters are utilized to contribute to the read and write operations, which results in a lower complexity. The peripheral circuitries are designed based on the gate-all-around carbon nanotube field-effect transistor (GAA-CNTFET). The hardware simulation results show a 5.2 times improvement (78% reduction) in power-delay product (PDP), on average, compared with the previous fully nonvolatile approximate full adders. Utilizing the approximate adders in Gaussian filters to denoise a noisy image revealed that our proposed adders result in almost the same image quality as an accurate adder. Both our adders have an accurate carry output and two erroneous sum outputs. Nevertheless, these two erroneous outputs have a low-value gap, which results in higher quality in image processing applications. The results indicate that the proposed designs make an effective tradeoff between energy and accuracy, which is the main goal of approximate computing.

Fundamental to digital signal processing applications such as the Arithmetic Logic Unit (ALU), logic gates serve as the foundational components. This paper presents NOR and NAND gates engineered for operation within the ultra-low voltage (LV) and low power domains (LP). Utilizing the floating gate MOSFET (FGMOS) approach, this study adopts a strategy to enhance performance, focusing on reducing design complexity and minimizing power consumption.The proposed FGMOS-NAND/NOR gate design is investigated for important device parameters such as power (pwr), delay (tp), power delay product (PDP), and energy delay product (EDP). At 0.7 V supply, the overall power consumption of the FGMOS NOR and NAND gates is 0.442 nW and 0.323 nW, respectively. Further, carbon nanotube field effect transistor (CNTFET) technology is used to implement NOR and NAND gates in this research work. A rigorous comparative analysis was conducted in this research study to assess the performance of non-conventional technologies, specifically field-effect transistors with floating gate (FGMOS) and carbon nanotube field-effect transistors (CNFET), in comparison to the conventional complementary metal-oxide-semiconductor (CMOS) technology. Notably, our investigation revealed that when carbon nanotube field-effect transistor (CNTFET) technology is synergistically employed in conjunction with FGMOS technology, the overall circuit performance is significantly enhanced. Furthermore, in order to estimate the robustness and reliability of the proposed designs, comprehensive analysis pertaining to delay and power-delay product (PDP) variability were meticulously carried out within the scope of this research article.

Approximate computing is an emerging approach for reducing the energy consumption and design complexity in many applications where accuracy is not a crucial necessity. In this study, ultra-efficient imprecise 4:2 compressor and multiplier circuits as the building blocks of the approximate computing systems are proposed. The proposed compressor uses only one majority gate which is different from the conventional design methods using AND - OR and XOR logics. Furthermore, the majority gate is the fundamental logic block in many of the emerging majority-friendly nanotechnologies such as quantum-dot cellular automata ( QCA ) and single-electron transistor ( SET ). The proposed circuits are designed using FinFET as a current industrial technology and are simulated with HSPICE at 7nm technology node. The results indicate that our imprecise compressor is superior to its previous counterparts in terms of delay, power consumption, power delay product (PDP) and area, and improves these parameters on average by 32%, 68%, 78%, and 66%, respectively. In addition, the proposed efficient approximate multiplier is utilized in image multiplying as an important image processing application. The HSPICE and MATLAB simulations indicate that the proposed inexact multiplier provides a significant compromise between accuracy and design efficiency for approximate computing.

Carbon nanotube field-effect transistors (CNFETs) are considered to be promising candidate beyond the conventional CMOSFET due to their higher current drive capability, ballistic transport, lesser power delay product and higher thermal stability. CNFETs show great potential to build digital systems on advanced technology nodes with big benefits in terms of power, performance and area (PPA). Hence, there is a great need to develop proven models and CAD tools for performance evaluation of CNFET-based circuits. CNFETs specific parameters, such as number of tubes, pitch (spacing between the tubes) and diameter of CNTs determine current driving capability, speed, power consumption and area of circuits and play a significant role in accurate PPA evaluation. Furthermore, count and density variations in carbon nanotubes (CNTs) due to manufacturing limitations, like the presence of metallic tubes in the CNFET channel, pose major obstacles to robust and energy-efficient CNFET digital circuit designs and degrade the anticipated PPA benefits. CNFET-based circuits can suffer from large performance variations and reduction in functional yield due to these variations in CNFETs. Moreover, modeling the CNFET parameters, CNT variations and etching techniques for CNTs create additional complexity during performance optimization. Hence, for realistic optimization of CNFET circuit's performance, it is imperative to incorporate the impact of these parameters and variations. We present a capacitance-based Logical Effort (LE) framework to investigate design issues of high-speed and low-power circuit designs implemented by considering specific requirements and challenges of the CNFET technology. The LE technique is widely recognized as a pedagogical method to quickly estimate and optimize the propagation delay and transition time in CMOS circuits equivalently without performing transient simulations and detailed delay calculations. In this thesis, we propose novel delay models [Pitch-Aware Logical Effort (PALE) and Position-Aware Pitch Factor (PAPF)] for fast and accurate performance evaluation by including the impact due to CNFET-specific parameters and CNT variations. 1. Ideal case (CNTs variations are not considered): During our research on CNFET-based circuits, we analyzed the impact of CNFET specific parameters, such as CNTs count, diameter and spacing between tubes, on the performance of CNFET-based circuits. The screening effect is critical to take into account for accurate performance evaluation. Hence, PALE model is developed by extending LE formulation to include influence of CNFET specific parameters. 2. Realistic case (CNTs variations are considered): We have studied CNFET-based logic gates and circuits in the presence of major CNTs variations using Monte Carlo simulations. The removal of the

Commonly used MR image quality (IQ) metrics have poor concordance with radiologist-perceived diagnostic IQ. Here, we develop and explore deep feature distances (DFDs)-distances computed in a lower-dimensional feature space encoded by a convolutional neural network (CNN)-as improved perceptual IQ metrics for MR image reconstruction. We further explore the impact of distribution shifts between images in the DFD CNN encoder training data and the IQ metric evaluation. We compare commonly used IQ metrics (PSNR and SSIM) to two "out-of-domain" DFDs with encoders trained on natural images, an "in-domain" DFD trained on MR images alone, and two domain-adjacent DFDs trained on large medical imaging datasets. We additionally compare these with several state-of-the-art but less commonly reported IQ metrics, visual information fidelity (VIF), noise quality metric (NQM), and the high-frequency error norm (HFEN). IQ metric performance is assessed via correlations with five expert radiologist reader scores of perceived diagnostic IQ of various accelerated MR image reconstructions. We characterize the behavior of these IQ metrics under common distortions expected during image acquisition, including their sensitivity to acquisition noise. All DFDs and HFEN correlate more strongly with radiologist-perceived diagnostic IQ than SSIM, PSNR, and other state-of-the-art metrics, with correlations being comparable to radiologist inter-reader variability. Surprisingly, out-of-domain DFDs perform comparably to in-domain and domain-adjacent DFDs. A suite of IQ metrics, including DFDs and HFEN, should be used alongside commonly-reported IQ metrics for a more holistic evaluation of MR image reconstruction perceptual quality. We also observe that general vision encoders are capable of assessing visual IQ even for MR images.

LAHAF: Low-power, area-efficient, and high-performance approximate full adder based on static CMOS