Abstract
As the gap between processor performance and memory latency widens, the computer architecture research area is always out for new solutions for efficient memory access. In this paper, we analyze the maximum achievable gain by simulating an ideal DRAM memory that always services requests as row buffer hits, thus minimizing memory access latency and queuing. We reproduced the state-of-the-art ConGen2 technique from Natale et al. to measure how much improvement is still available. ConGen2 minimizes row buffer misses according to a min-k-cut solution based on all memory accesses of a target application. We observed that ConGen2 improves memory usage by 2.30% on average, while the ideal memory gains 36.88% on average for the chosen benchmarks. This gap leaves a wide margin of benefits to be gained.
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