Measurement of partial charge collection in a soft X-ray optimised backside illuminated CMOS image sensor

BackSide-Illuminated (BSI) CMOS Image Sensors (CISs), with developed performance on quantum efficiency and sensitivity, have been applied for aerospace missions and gradually replaced FrontSide-Illuminated (FSI) CISs. Two types of BSI CISs with different epitaxial layer thicknesses were irradiated by 14-MeV neutron up to 3.40 × 1011 n/cm2 to analyze the degradation induced by neutron irradiation. Dark current, dark current distribution, full well capacity, and spectral response were tested before and after the neutron irradiation and at different annealing time points with various temperatures. The results were analyzed to characterize the degradation introduced by the unique backside passivation layer, and the converse illuminated direction. The interface states induced by displacement damage effects at the backside passivation layer were considered as a novel origin of dark current which was not involved in FSI CISs.

A novel low cost backside illuminated CMOS image sensor structure is proposed in this research. By using thin wafer handling technology, the wafer is thinned down to less than 5 μm and no TSV and direct bonding process are needed in this low cost solution. The processed backside illuminated CMOS image sensor is then stacked with analog to digital conversion chip and image signal processor by 3DIC technology. A 3-Mega pixel image is captured and demonstrated in this research.

In this study, a back-side illuminated CMOS image sensor (BSI-CIS) without through-silicon via (TSV) is developed with thin wafer handling combination with ultra-wafer thinning technologies. The CIS wafer is implemented front-side processes then temporarily bonded on a Si carrier by Brewer Science adhesive with ZoneBOND™ technology applied. The ZoneBOND™ technology provides a promising solution for thin wafer handling with temporary bonding, wafer thinning, thin wafer processes, and de-bonding. After thinning, the CIS backside is bonded with glass wafer, and the Si carrier is removed using solvent dipping for de-bonding. The thickness of BSI-CIS without TSV is less than 5μm, which is visible light transparent to meet the back-side illumination requirement. Cu/Sn bumps with 50μm size are formed with the bump height uniformity less than 5% in wafer level. The completed BSI-CIS is then assembled on Si substrate. There are totally 400 bumps in this test vehicle design. The Cu/Ni/Au UBMs on Si substrate bonded with Cu/Sn bumps on CIS is conducted by thermal compression bonding. The wafer-level package of TSV-less BSI-CIS has been successfully developed and demonstrated, stacked module is accomplished and passed 1000 cycles of -55°C~125°C TCT in the paper.

A study of the mechanism of proton irradiation effects in the in-orbit operation of the backside illuminated CMOS image sensor (BSI CIS) used for imaging by the Fine Guidance Sensor (FGS) is presented in this paper. According to the proton irradiation environment of the Halo L2 orbit where FGS is located and the duration of in orbit operation, proton irradiation experiments were conducted on the BSI CIS, the core imaging device of FGS. Results show that proton irradiation is expected to cause a significant increase in the dark current of the BSI CIS of the FGS after four years of its in orbit, with the peak of the dark signal distribution shift to the right and an exponential trailing of the tail of the dark signal distribution when the proton fluence reached 6.71 × 1010p/cm2. This is the result of a combination of ionization defects and displacement damage defects. In addition, we also report about the device gain, which is of particular interest in space astronomical exploration. We performed a more detailed single pixel gain test of the device gain and found that the degradation of the gain appears to be correlated with the intensity of the ionization defects. The results of this study can provide theoretical basis for the radiation hardening by design of FGS to some extent.

Study of dark current random telegraph signal in proton-irradiated backside illuminated CMOS image sensors

Backside illuminated CMOS image sensors with a 3D stacked architecture, where the pixel array is attached on top of the logic circuit, was introduced and have just come to the market. Image sensor featuring 3D stacking was realized by connection between the interconnect layers of the top and bottom parts using vertical type through-silicon via (TSV).1 Cu bonding technology for 3D integration has been studied and widely applied.2As Wafer-to-wafer bonding process is now being used widely and matured through the production of Backside illuminated CMOS image sensors, Copper-copper bonding provides an attractive route to 3D stacked image sensor since it creates a strong metal bond and enables vertically electrical connection during the bonding process.Specific pre-bonding surface conditioning is necessary to insure high bonding quality of patterned Cu wafers using Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking. Surface preparations for the hybrid fusion bonding such as removal of Cu oxide, Cu surface protection and optimized CMP planarization patterned Cu surfaces have been studied,3 but the study on plasma condition for hybrid fusion bonding is relatively a few. The work described here is investigating of the plasma-related Cu patterned hybrid surface preparation under different plasma conditions.The main physical mechanisms about Cu-Cu non thermal compression bonding are spontaneous adhesion of hydrophilic surfaces followed by Cu diffusion across the bonding interface when Cu-Cu contact is reached (diffusion bonding) have been previously reported.4 The property of Cu dielectric diffusion barriers used in ULSI is hydrophobic. For the efficient bonding of hydrophobic-hydrophobic layers, surface conversion process is introduced.5 In the case of Cu-patterned hybrid bonding in typical Cu metallization layer in ULSI, Trade-off between dielectric diffusion barrier and Cu cannot be avoidable by surface conversion process.During the Cu-patterned hybrid bonding development, the common electrical failed areas were found.To investigate the failure mechanism, influence of plasma condition on the activation of wafer surface and bonding quality was studied. The wafer surface was examined by X-ray photoelectron spectroscopy (XPS), surface roughness, and observation of differential work function uniformity over a full wafer area caused by plasma-induced charge.6The ChemetriQ NVD inspection system from Qcept Technologies was used to inspect differential work function uniformity.After implementing plasma treatment applied in bonding process, Non-uniformity of a charge map and different plasma influence over a full wafer area were shown, even there was no difference through the AFM analysis. For the optimization of the bonding process, especially plasma process, a method to examine the surface condition in this paper makes it possible to monitor the plasma process and improve bonding process

As CMOS image sensors continuously scale down, random telegraph noise (RTS) has become a more and more important consideration. In this paper, significant reduction of RTS is achieved by optimizing the deep trench isolation (DTI) process for backside illuminated CMOS image sensor (BSI).

A novel phase-detection auto focus (PDAF) technique for incident 850 nm plane wave is demonstrated using Ge-on-Si layer and deep trench isolation (DTI), which are locally arranged on light receiving surface (LRS) of crystalline silicon (c-Si). No metal light shielding film (LSF) for pupil division is formed. The key concept of the present work for PDAF is to perform the pupil division by the locally arranged Geon-Si layer in a pixel according to incident angle. The present pixel is based on a back-side illuminated CMOS image sensor pixel; the pixel pitch is 1.85 μm and the thickness of c-Si is around 3 μm. The simulation, based on three-dimensional finite difference time domain (3D-FDTD) method, shows that the external quantum efficiency (EQE) of the present pixel exhibits above 44.3 % with the maximum of 76.0 % for incident angles of - 30° to + 30°, owing to the selectively arranged Ge-on-Si layer; it exhibits 3.6 times improvement in the EQE at normal incidence compared to that of current state-of-the-art pixel with half metal-shielded aperture; the EQE is 49.2 % and 13.8 %, respectively. The present technique can enhance the accuracy of AF under low-illuminated condition.

We have developed a compliant bump technology for 3D chip stacking with the same number of inter-chip connections as that in a VGA (video graphic array, 640 × 480). Using this technology together with a through-Si via (TSV) technology, we demonstrate a prototype of back-side illuminated CMOS image sensor, in which a very-thin rear-illuminated photodiode array is electrically connected to the CMOS readout circuit at a pixel level.

In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of a 3 Mega pixel CMOS image sensor is temporary bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to few microns to detect the light from the backside. The backside is then permanently bonded to a glass carrier substrate with a transparent thermal set bonding material. After the glass permanent bonding process, the temporary bonded silicon carrier could be removed. Cu/Sn micro-bump is fabricated at the front-side of the CMOS image sensor, thus no TSVs are needed in the proposed structure. A 3 Mega pixel CMOS wafer with micro-bumps bonded on 500µm-thick glass wafer is demonstrated. Void-free bonding is obtained both in temporary bonding and permanent bonding processes. The thickness of the CMOS image sensor wafer is less than 10 µm after thinning and the total thickness variation is around 1 µm. Thermal plastic material is used for temporary bonding because it flows during bonding process and resulted in excellent planarization. From the cross-section SEM image, Cu/Sn micro-bump is formed at the front-side of the CMOS image sensor and the ENIG UBM is formed on the front side of the Analog-to-Digital Conversion wafer. A 3 Mega pixel image is captured and demonstrated in this research. The proposed backside illuminated CMOS image sensor structure and process integration are processed in wafer level, therefore enabling a low cost technology which can be manufactured using existing infrastructure. By using thin wafer handling technology, direct fusion bond and TSV processes are not needed which provides a low cost wafer level solution.

In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of a 3 Mega pixel CMOS image sensor is temporary bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to less than 5 μm for light detection from the backside. After thinning process, the backside is permanently bonded to a 500μm-thick glass carrier substrate with a transparent thermal set bonding material. After thinning, the total thickness variation of 1μm is obtained because the thermal plastic material flow during bonding process resulted in excellent thickness uniformity. The proposed backside illuminated CMOS image sensor structure and process integration are processed in wafer level, therefore enabling a low cost technology which can be manufactured using existing infrastructure. In the assembly process of CMOS image sensor stack, firstly the analog-to-digital conversion chip was stacked onto the image signal processor chip by thermal compression bonding. Optimized bonding conditions of 250 °C/5 sec under the bonding force of 13N were chosen and determined. Subsequently, after the stack of analog-to-digital conversion chip onto the image signal processor chip, the CMOS image sensor chip was bonded onto the image signal processor/analog-to-digital conversion stack. To connect all the solder bumps between CMOS image sensor and analog-to-digital conversion chip, the higher bonding force of 18N was selected. Joined-well solder joints between these two chips could be achieved. Finally, the stacked CMOS image sensor module was attached to a print circuit board by adhesive material and wire bonding was conducted to finish the electrical connectivity between CMOS image sensor stack and print circuit board.

1.12μm backside illuminated CMOS image sensor with backside deep trench isolation (DTI) has been demonstrated for the first time. DTI is fabricated on backside pixel surface after wafer bonding and grinding process. Backside DTI makes its layout simple because no transistor isolation exists on backside. We have confirmed about 50% reduction of crosstalk by using backside DTI. The crosstalk of 1.12μm backside DTI pixel is lower than that of 1.4μm BSI pixel. This technology will be promising for 1.12μm and beyond.

In this research, a backside illuminated CMOS image sensor (BSI-CIS) without through-silicon via and TSV based Si interposer are developed with thin wafer handling technology. The BSI-CIS wafer is implemented front-side processes then temporary bonded on a Si carrier by using ZoneBOND™ technology. After thinning, the CIS backside is bonded with glass wafer, and the Si carrier is removed using solvent dipping for de-bonding. The thickness of BSI-CIS without TSV is less than 5um, which is visible light transparent to meet the back-side illumination requirement. TSV fabrication, void-free TSV filling, bumping, wafer thinning, thin wafer handling and backside RDL formation are well developed and 30um TSV, 60um thin wafer have been successfully integrated to Si interposer. Cu/Sn bumps with 50μm size are formed with the bump height uniformity less than 5% in wafer level. The wafer-level package of BSI-CIS and TSV based Si interposer have been successfully developed and demonstrated, the characterization results of three layer stacked module is also disclosed in the paper.

CMOS detectors offer many advantages over CCDs for optical and UV astronomical applications, especially in space where high radiation tolerance is required. However, astronomical instruments are most often designed for low light-level observations demanding low dark current and read noise, good linearity and high dynamic range, characteristics that have not been widely demonstrated for CMOS imagers. We report the performance, over temperatures from 140 - 240 K, of a radiation hardened SRI 4K×2K back-side illuminated CMOS image sensor with surface treatments that make it highly sensitive in blue and UV bands. After suppressing emission from glow sites resulting from defects in the engineering grade device examined in this work, a 0.077 me⁻/s dark current floor is reached at 160 K, rising to 1 me⁻/s at 184 K, rivaling that of the best CCDs. We examine the trade-off between readout speed and read noise, finding that 1.43 e⁻ median read noise is achieved using line-wise digital correlated double sampling at 700 kpix/s/ch corresponding to a 1.5 s readout time. The 15 ke⁻ well capacity in high gain mode extends to 120 ke⁻ in dual gain mode. Continued collection of photo-generated charge during readout enables a further dynamic range extension beyond 10⁶ e⁻ effective well capacity with only 1% loss of exposure efficiency by combining short and long exposures. A quadratic fit to correct for non-linearity reduces gain correction residuals from 1.5% to 0.2% in low gain mode and to 0.4% in high gain mode. Cross-talk to adjacent pixels is only 0.4% vertically, 0.6% horizontally and 0.1% diagonally. These characteristics plus the relatively large (10μm) pixel size, quasi 4-side buttability, electronic shutter and sub-array readout make this sensor an excellent choice for wide field astronomical imaging in space, even at FUV wavelengths where sky background is very low.

Backside illuminated CMOS image sensors were developed in order to encompass the pixel area limitation due to metal interconnects. In this technology the fully processed CMOS wafer is bonded to a blank carrier wafer and then back-thinned in order to open the photosensitive sensor area. The process flows of the two main competing wafer bonding technologies used for this manufacturing process (adhesive bonding and low temperature plasma activated direct wafer bonding with polymer layers) will be reviewed.