Measurement of Circuit Parasitics of SiC MOSFET in a Half-Bridge Configuration

Abstract

Fast switching transient of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> reduces switching loss. However, it excites device and circuit parasitics resulting in prolonged oscillation, high device stress, spurious turn <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> , EMI related issues, and higher switching loss. Behavioral or analytical models are used to estimate switching loss <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$(dv/dt)$</tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$(di/dt)$</tex-math></inline-formula> rates, etc., and it requires the value of circuit parasitics as input. Measurement is the only way to accurately estimate some device package-dependent circuit parasitics when the internal package geometry is unknown. Hence, measurement of circuit parasitic is essential for optimal design. This article presents a set of simple experimental measurement techniques to determine circuit parasitic inductance and capacitances relevant for switching transient study of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> in a half-bridge configuration. The accuracy of the proposed technique is verified through simulation and experimental results of the hard turn <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> and capacitor assisted soft turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> dynamics of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> over a range of operating conditions for two 1.2-kV discrete SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> of different current ratings and two different PCB layouts. Furthermore, the proposed technique is also validated with the existing frequency response analysis-based impedance measurement.