Abstract
A new algorithm for general area multichip module routing using a multi-candidate and compatibility graph approach, which maximises routing density while minimising vias and total wire length, is presented. Experimental results using standard industrial benchmarks show improved results relative to a commercial router and other previously proposed routers while offering flexibility for future incorporation of noise and delay constraints.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
