Abstract
Variable Length Codes (VLC) are used to transfer same amount of digital information in relatively short period of time. In variable length coding, the characters with higher probability of occurrence are assigned shorter bits sequence and the characters with less probability of occurrence are assigned relatively longer bits sequence. However, due to variable length nature of codes, the decoding circuitry at the receiving end loses the synchronization due to single or multiple bit inversions. This typically happens when data is transmitted through a Binary Symmetric Channel (BSC). This paper investigates synchronizing scheme to control the error propagation due to single or multiple bit inversions through BSC. The hardware implementation of the proposed algorithm has been presented using a hardware description language. The functional level simulation of the implementation is discussed to test the proposed algorithm.
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