MACHINE LEARNING ASSISTED ANALOG LAYOUT SYNTHESIS FOR ADVANCED RF FRONT ENDS

As semiconductor manufacturing migrates to more advanced technology nodes, the performance improvement anticipated from scaling has failed to match expectations. This failure is due to the emergence of layout-dependent effects (LDEs) not encountered in the design flow prior 65nm process node. We propose a novel methodology that allows the early detection of LDEs during schematic creation. Different from all previous works, this methodology accurately calculates LDEs by interfacing interactively with a simulator tool. Our research indicates that no previous works suggested the use of "on-the-fly" simulation, using Eldo Interactive, to study LDEs. In fact, the use of Calibre tools [2] has been suggested to help the designer check certain basic electrical constraints (like matching) under the existence of LDEs, by specifying the matching condition as a comment added to the original Pyxis schematic netlist. [1] These comments are then transformed into verification rules that are added and checked by Calibre. The proposed flow is tested on a 40nm OTA design, with results not only as accurate as those previously obtained from post-layout analysis, but also equal to or better speed of execution, demonstrating the practicality of using "on-the-fly" simulation to detect and resolve LDEs early in the design flow.

Performance degradation in analog circuits due to layout dependent effects (LDEs) has become increasingly challenging in advanced technologies. To address this issue, LDEs have to be seriously considered as performance constraints in the physical design process. In this article, we have proposed an innovative LDE-aware retargeting methodology for analog layout migration from old technologies to new ones with LDEs optimized for performance preservation. The LDE constraints, which are first identified with the aid of a specialized sensitivity analysis scheme, are satisfied during the layout migration process. Moreover, optical proximity correction (OPC), as one of the most popular resolution enhancement techniques for subwavelength lithography in modern nanometer technology manufacturing, is also included in this study. We have developed an OPC-inclusive ILP-based analog router to route electrical nets for improving image fidelity of the final layout while the routability and other analog constraints are respected in the meantime. The experimental results show our proposed layout migration methodology along with the routing scheme is able to retarget analog layouts with better circuit performance and finer image quality compared to the previous works.

The frequency bands below 3 GHz are occupied by various wireless applications. The overcrowding of many applications in these bands is the primary source of distortion in the wireless system. To combat distortion in the system, the radio frequency (RF) blocks must satisfy the linearity requirements of the application. Hence, in this paper, a high linear wideband low noise amplifier (LNA) stage is proposed for RF front-end. The LNA uses the combination of common-gate (CG) and common-source (CS) stages for cancelling the noise and distortion of the input matching CG stage. The CS stage exploits complementary derivative superposition (CDS) for linearity improvement, and cross-coupled local feedback network is employed for noise cancellation at the output. The LNA stage is designed using UMC 180 nm CMOS process technology and post-layout characterizations are carried out using Cadence SpectreRF circuit simulator. Also, the process corner, voltage, and temperature (PVT) variation analysis and Monte-Carlo simulations for mismatch analysis are carried out to verify the reliability of the LNA. The designed LNA has an input referred third-order intercept point (IIP3) of 8.85 dBm. The proposed LNA has a maximum gain of 23.96 dB and minimum noise figure (NF) of 1.4 dB with a total current consumption of 3.1 mA from a 1.8 V supply.

With the increased device integration density in advanced semiconductor technologies, the layout-dependent effects (LDEs) have become critical affecting both device-level and circuit-level performance. In this brief, we report an impact study of LDEs on 14-nm FinFET combinational standard cells to facilitate the process of design-technology co-optimization (DTCO). Focusing on the poly pitch, cut poly effect, oxide spacing effect, and cell height, improvement in speed and power consumption of typical 14-nm FinFET combinational standard cells has been achieved. Seven standard cell libraries are further designed and constructed based on the LDE study, enabling comprehensive applications with different performance, power and area (PPA) preference. Such DTCO and demonstrated experimental results can be attractive in future customized designs employing the enriched standard cell libraries at advanced technology nodes.

Layout-dependent effects (LDEs) have become a critical issue in modern analog and mixed-signal circuit designs. The three major sources of LDEs, well proximity, length of oxide diffusion, and oxide-to-oxide spacing, significantly affect the threshold voltage and mobility of devices in advanced technology nodes. In this paper, we propose the first work to consider the three major sources of LDEs during analog placement. We first transform the three LDE models into nonlinear analytical placement models. Then an LDE-aware analytical analog placement algorithm is presented to mitigate the influence of the LDEs while improving circuit performance. Experimental results show that our placement algorithm can effectively and efficiently reduce the LDE-induced variations and improve circuit performance.

As process technologies continually advance, process variation has greatly increased and has gradually become one of the most critical factors for IC manufacturing. Furthermore, these increasingly complex processes continue to make greater use of stressors for mobility enhancement, thus requiring large volumes of data for extensive characterization of layout-dependent effects (LDE) for validation of both SPICE models and design for manufacturing. Transistor threshold voltage (Vt) is a commonly used parameter both for characterization during process development and for monitoring of volume manufacturing. To adequately quantify local process variation or LDE, Vt must be measured for a sufficiently large number of device-under-tests (DUTs) to obtain a statistically representative sample population. The number of Vt measurements required to obtain such a statistically significant result, however, requires extremely long testing time, especially for array-based test structure designs including thousands of DUTs. In this paper, we present a very fast threshold voltage measurement methodology using an operational amplifier-based source-measure unit test configuration, which greatly improves testing efficiency and accuracy, and is not sensitive to process variation. The proposed test methodology can improve Vt testing time by a factor of 5-10 relative to the commonly used binary-search algorithm, and by a factor of ~2 relative to an optimized interpolation algorithm, and achieves better accuracy (standard deviation of Vt = 0.15 mV, versus typical accuracy of ~ 0.5 mV for the two algorithms mentioned). Furthermore, the layout and configuration of conventional test structures need not be modified to adapt the proposed methodology. The measured results from the most advanced process technology nodes demonstrate the testing efficiency and accuracy of the proposed test structure in characterizing the large number of DUTs required for quantifying process variation or LDEs.

Analog and mixed-signal integrated circuits play an important role in many modern emerging system-on-chip (SoC) design applications. With the expansion of the markets of those applications, the demands of analog/mixed-signal ICs have been dramatically increased. Although analog/mixed-signal ICs have gained more and more importance and demands in modern SoC applications, the development of analog electronic design automation (EDA) tools is still farther behind that of digital EDA tools. As a result, analog/mixed-signal IC design, especially the analog layout design, is still a manual, time-consuming, and error-prone task. In order to speed up modern SoC design for large varieties of emerging applications, it is desirable to develop novel analog/mixed-signal IC deign methodologies and algorithms, as well as new analog EDA tools. The purpose of this paper is to summarize recent research progress during the past decade, address new analog layout design challenges in advanced technology nodes, and facilitate more research activities in analog layout synthesis.

As device dimension shrinks less than 65nm, the propagation delay, crosstalk noises, and power dissipation due to RC (Resistance Capacitance) coupling becomes significant. Cu and LK (Low-k dielectric) material have been introduced to reduce such delays and allow higher device speed and better performance. However, since dielectric material with low-k value usually possesses large amount of porosity, its mechanical properties are degraded significantly which leads to fragile silicon backend structure. This in turn brings in reliability issues like LK cracking due to CPI (Chip Package Interaction). The application of flip-chip packaging introduces significant amount of mechanical stress on BEOL (Back-End-Of-Line) at chip-attach processing step due to CTE mismatch, and makes CPI much more challenging and critical for silicon integration. At advanced technology nodes, increasing performance demand of mobile processors coupled with SoC integration is one major driver of bump pitch reduction [1]. Higher I/O count can be achieved with finer bump pitch since die size very likely stays constant if not shrinking further. Cu pillar and ELK material have been introduced in 28nm to realize the pitch reduction and performance gain. Small UBM structure is required with fine pitch Cu pillar which introduces large amount of stress in BEOL layers. On the other hand, while k-value of ELK is reduced by ~20% compared to LK used in previous technologies, its hardness and mechanical modulus have been reduced by ~30%, resulting in major reduction of ELK material strength. In this paper, we present our key learnings from 28nm CPI development with fine pitch Cu pillar. Empirical data based on CPI TV as well as mechanical stress simulations are discussed. UBM dimension which is a critical factor with Cu pillar from CPI perspective is searched at fine pitch, and our data shows CPI robustness limits pitch reduction with Cu pillar if using standard mass reflow process. ELK robustness is also tested at different process corners, including UBM size, bump height and Cu etching module. Some ELK marginality issues are discovered at certain process corner combinations. CPI margin at 28nm with fine pitch Cu pillar is then assessed by correlating mechanical stress simulation to thermal shock testing data. It is shown that min ~15% ELK margin in terms of max ELK stress is necessary to ensure no ELK delamination happening at process corners. Impact of IMC (Intermetallic Compound) and Ni barrier are also studied. It is found that growth of IMC is critical for ELK integrity with mass reflow process. Once IMC is fully grown between Cu pillar and substrate bonding pad, since its stiffness is 2~3X higher than Lead-free solder, mechanical stress on ELK layers increases dramatically. Additional work is carried out to minimize the growth of IMC. It is confirmed that addition of Ni barrier effectively suppresses IMC growth, and increases CPI margin at process corners by considerable amount. Detailed data is presented and final recommendations on fine pitch Cu pillar conclude the paper.

PVT-compensated low voltage LNA based on variable current source for low power applications

Standard cell layout in advanced technology nodes are done manually in the industry today. Automating standard cell layout process, in particular the routing step, are challenging because of the constraints of enormous design rules. In this paper we propose a machine learning based approach that applies genetic algorithm to create initial routing candidates and uses reinforcement learning (RL) to fix the design rule violations incrementally. A design rule checker feedbacks the violations to the RL agent and the agent learns how to fix them based on the data. This approach is also applicable to future technology nodes with unseen design rules. We demonstrate the effectiveness of this approach on a number of standard cells. We have shown that it can route a cell which is deemed unroutable manually, reducing the cell size by 11%.

At advanced integration nodes, the impact of layout-dependent effects (LDEs) turn the performance of MOSFET devices strongly dependent on the layout implementation details, but also, of its surrounding neighborhood. However, in the traditional design flow, the real LDEs-impact is only known after complete extraction and post-layout simulation, causing re-design iterations with no valuable feedback information to fix the problem. This paper proposes an automatic placement methodology for analog integrated circuit (IC) layout design, that minimizes the mobility and threshold-voltage-related variations caused by the two major sources of LDEs above the 40 nm technology nodes, i.e., well-proximity effect and length of oxide diffusion. An absolute representation of the floorplan is adopted, and, a multi-objective optimization (MOO) algorithm with LDE-impact mitigation operators, is applied. Established LDE formulations used in BSIM models are used to guide placement optimization, shorting the gap between pre and post-layout performance.

Application of reinforcement learning to deduce nuclear power plant severe accident scenario

Advancements in technology and numerical methods have shifted from slow, resource-intensive software to faster predictive solutions powered by artificial intelligence (AI). An exemplary case is the analysis of interference fit connections between a cylindrical shaft and hub, which has the potential to redefine optimal design, minimizing stress and maximizing torque transmission. Traditional experimental analysis using Finite Element Method (FEM) simulations is undeniably time-consuming, inefficient, and complex, thus necessitating the deployment of AI as a pivotal tool in industrial applications. This paper unequivocally introduces a cutting-edge technique that harnesses two powerful AI approaches: Supervised Learning and Reinforcement Learning. The Reinforcement Learning approach expounded in this paper impeccably predicts the shaft-hub geometry set, eliminating the need for iterative simulations and drastically streamlining the optimization process. In order to address this challenge, a Supervised Learning model is rigorously trained using limited data obtained from experimental structural analysis. Subsequently, the predictions from this model serve as the environment for the Reinforcement Learning (RL) algorithm. The customized environment in Reinforcement Learning ingeniously employs the model to refine predictions by adjusting the input parameters for different geometric sets through respective actions on the environment.

Process parameters, e.g., transistor width, may greatly vary not only across multiple manufacturing lots, but also within the same die from the same manufacturing lot. In addition to process variations different parts of a chip may see different voltages and temperatures. These process-voltage-temperature (PVT) variations are termed as On-Chip Variations (OCV) and can unsystematically affect wire and cell delays. This variability is accounted for by adding OCV de-ratings to path delays during static timing analysis (STA), where the original timing values are split into early (lowerbound) and late (upperbound) quantities. Chip timing is then done against these new delays to ensure safe chip operation. Any unknown or hard-to-model variation effect can also be margined for in these OCV de-ratings. However, this additional pessimism can significantly increase the difficulty to achieve timing closure, thereby elongating the design cycle and time to market. In particular, excess pessimism along clock network creates the most design-cycle churn, as pessimistic clock delays impact nearly all data paths. This session discusses the overview and challenges of common path pessimism removal (CPPR), the method of safely removing excess pessimism from clock paths, from an industry perspective.

A single-to-differential low-noise amplifier (LNA) is proposed for low-power medical devices in the frequency band of 401-406 MHz. The proposed LNA avoids the use of surface acoustic wave (SAW) filter and additional balun in RF receiver front-end. The LNA comprises inductive degeneration common source (IDCS) technique (stage I) and a cascaded common source circuit (stage II). The stage-II is stacked on top of stage-I. The proposed balun LNA incorporates single to differential (SD) conversion for minimum gain and phase error. A compensation bias circuit is proposed to minimise variations in parameters of LNA against process corners, supply voltage and temperature (PVT). An upsurge balun LNA is designed in UMC 0.18-μm CMOS technology, the DC power consumption is 290 μW under a supply voltage of 1 V and the minimum noise figure is 3 dB. The die area of LNA including buffers and bias circuit is 850 μm × 978 μm. The worst-case post layout simulation results show a gain and phase error of 0.8 dB and 10°. The percentage variation of gain and NF against PVT is reduced by 55 and 48%. Furthermore, the balun LNA has out of band rejection at the roll-off rate better than 70 dB/dec.