Lumped-Element Wilkinson Power Combiners Using Reactively Compensated Star/Delta Coupled Coils in 28-nm Bulk CMOS

Abstract

This paper presents four compact lumped-element Wilkinson power combiners (WPC) operating at 5 GHz in 28-nm bulk CMOS. To minimize the chip area, the inductances in the designs are implemented using mutually coupled coils. Two designs use star inverting coupled coils (SICC), while the other two employ delta noninverting coupled coils (DNICC). One of the two SICC-based designs (and similarly for the DNICC-based designs) incorporates a second harmonic (2f0) trap to lower the total harmonic distortion and reduce the required inductances by 25%, further reducing the circuits footprint. A design methodology for effectively exploiting the mutual coupling and nullifying the coupling parasitics is presented. The coupling parasitic in the DNICC-based design is exploited to provide the WPC isolation resistance, resulting in a lumped-element WPC requiring only three components: a coupled coil and two capacitors. The measurement and simulation results are presented to confirm the theory validity. The SICC-based WPC with an area of 0.13 mm2 achieved input return losses (RL) >17.5 dB, output RL > 11.8 dB, isolation >11.2 dB, and insertion losses (IL) 18.2 dB, output RL >11.6 dB, isolation >11 dB, IL 10 dB, output RL >15.3 dB, and IL 10.1 dB, output RL >14.6, IL <1.2 dB, and peak 2f0 rejection of 23 dB at 10.4 GHz in an area of 0.09 mm2.