Low-Voltage Process Technology

Abstract

This chapter serves as an introduction to IC fabrication of CMOS bulk, bipolar BiCMOS and CMOS SOI devices including sub-micron devices for low-voltage applications. Section 2.1 is a review of CMOS process technologies. Examples for an N-well CMOS process and a twin-tub CMOS process are considered. Section 2.2 deals with bipolar technology with emphasis on advanced bipolar structures. The topic of the isolation techniques used for both bipolar and CMOS is addressed in Section 2.3. In Section 2.4 we discuss the similarities between advanced CMOS and advanced bipolar transistor structures to demonstrate how both technologies are indeed converging. The BiCMOS technologies are introduced in Section 2.5. with emphasis on CMOS-based processes. Three BiCMOS technologies, with different performance/cost, are presented. Section 2.6. introduces a complementary BiCMOS structure, where a vertical isolated PNP transistor is merged with an NPN transistor in a CMOS process. In Section 2.7, a table with the design rules of a generic 0.8 µm BiCMOS process is supplied. Finally, in Section 2.8, SOI technology is reviewed for low-voltage applications.