Abstract
An InP HBT 1:4 demultiplexer IC with a multiphase clock architecture is described that reduces the number of circuit elements and power consumption while maintaining operating speed. The IC operated at 50 Gbit/s with 1.17 W power consumption at a supply voltage of −4.5 V. Compared to an IC with a conventional tree-type architecture using the same InP HBTs, the power consumption is less than half while the operating speed of 50 Gbit/s is maintained.
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