Abstract
Digital hearing aids can be made less expensive if they are reconfigurable and of low hardware complexity. Hence, this work proposes a hardware-efficient, reconfigurable filter bank structure, based on fractional interpolation. The proposed structure is reconfigurable since a single structure can be used for different patients with different types of hearing impairments. The proposed structure consists of a masking stage and a scheme generation stage with a prototype filter in each stage. The prototype filters are made multiplier-less by representing their coefficients in the CSD space. The filter characteristics are improved by deploying a MOABC optimization algorithm. The number of adders is reduced using the SIDC-CSE technique. The low-complexity structure can be used for all types of hearing impairments, with the matching error and delay within tolerable ranges. The proposed structure has been implemented on an FPGA to support the analytical results for low hardware complexity and hence low power.
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