Abstract
In this paper we report data on NMOS devices with ultra thin oxide (t/sub ox/=2 nm) and heavily doped substrates, showing, for the first time, that the gate current, for very low biases (-|V/sub FB/|<V/sub G/<0) cannot be explained by direct tunneling, but features an additional component which we attribute to gate electron tunneling into the anode interface states. Comparing measurements with simulations it is shown that this extra current can be used to estimate the interface states (D/sub it/) and to monitor oxide degradation in ultra thin oxides where the traditional stress induced leakage current due to bulk traps (SILC) is not detectable.
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