Low-Voltage Analog Switch in Deep Submicron CMOS: Design Technique and Experimental Measurements

Abstract

This paper concerns the design, implementation and subsequent experimental validation of a low-voltage analog CMOS switch based on a gate-bootstrapped method. The main part of the proposed circuit is a new low-voltage and low-stress CMOS clock voltage doubler. Through the use of a dummy switch, the charge injection induced by the bootstrapped switch is greatly reduced resulting in improved sample-and-hold accuracy. An important attribute of the design is that the ON-resistance is nearly constant. A test chip has been designed and fabricated using a TSMC 0.18 μm CMOS process (single poly, n-well) to confirm the operation of the circuit for a supply voltage of down to 0.65 V.