Low-Temperature Silicon Oxide Offset Spacer Using Plasma-Enhanced Atomic Layer Deposition for High-k/Metal Gate Transistor

Abstract

We have investigated the characteristics of silicon oxide films deposited by plasma-enhanced atomic layer deposition (PEALD) and plasma-enhanced chemical vapor deposition (PECVD) as offset spacer films of high-k/metal gate stacks. From the results of bonding structure analysis, the silicon oxide film deposited by PEALD has been found to be composed of a Si–O bond network of the stoichiometric silicon oxide film. On the other hand, the silicon oxide film deposited by PECVD is considered to contain suboxide bond structures. From the results of physical and mechanical evaluations, the silicon oxide film deposited by PEALD exhibits a lower wet etch rate, a higher film density, a lower dielectric constant, a smaller amount of water in the film, and a higher elastic modulus than that deposited by PECVD. PEALD showed excellent thickness controllability. From these results, the silicon oxide film deposited by PEALD has higher quality and is more suitable for use as an offset spacer than that deposited by PECVD. X-ray photoelectron spectroscopy showed that the surface oxidation of a titanium nitride film, which is used as a metal gate electrode, during PEALD can be suppressed by using a lower PEALD temperature. Finally, we have demonstrated that the drain current of a high-k/metal gate transistor with a silicon oxide offset spacer deposited by PEALD is markedly increased, compared with that with a high-temperature-deposited silicon oxide offset spacer.