Low-Temperature Self-Aligned-Silicide-Capable Transistor Process Using Solid-Phase-Epitaxy and Lift-Off for Hybrid Substrates

Abstract

Details of a large-area-compatible sub-600 °C process for the fabrication of high mobility field-effect transistors on single crystalline silicon are presented. It is shown that lift-off and solid-phase-epitaxy (SPE) can be used in conjunction with plasma enhanced chemical vapor deposition (PECVD) to create MOSFET transistors with mobilities comparable to other high-performance techniques. Furthermore, use of an amorphous silicon/silicon oxynitride (SiOxNy) sacrificial bilayer is shown to make the process capable of self-aligned silicidation. The topography of the deposition is studied using cross-sectional scanning electron microscopy (SEM). It is shown that a successful lift-off can be achieved through the proper design of the sacrificial bilayer despite the high degree of step coverage generally exhibited by PECVD films. Cross-sectional transmission electron microscopy (TEM) is used to reveal the microstructure of the epitaxy and silicidation. Current-voltage characteristics of the fabricated transistors are presented and the field effect mobility of electrons on the fabricated devices is reported. The developed process is particularly useful in applications where high mobility transistors need to be built on silicon/nonsilicon hybrid platforms that exclude high processing temperatures.