Low Power, Highly Stable and Enhanced Read Speed 7T SRAM

Abstract

Cache memory is one of the most important functional part of any system ranging from System on Chips (SoC) to personal computers. The cache memories are composed of millions of SRAM cells. Thus, for the cache memory to be reliable, it is important that SRAM cells have some specific features such as: high stability of the data retained, low static and dynamic power consumption, low read delay. As an attempt to accomplish the incorporation these features, a novel SRAM cell consisting of 7 transistors is proposed in this paper. The cell has separate bitlines for the read and write operation thereby isolating the two operations. Also, the storage node formed by the back-to-back inverters are not disturbed by read operation, this leads to enhanced robustness of data stored. The cell also makes use of dual Vt(threshold voltage) transistors in order to minimize leakage power consumption. Transistors in the cell is configured in such a way that there are minimum number of transistors in the read critical delay path, thereby reducing the read delay. Performance of the proposed model is compared with that of the conventional 6T SRAM cell to showcase the enhancements obtained.