Low energy high speed reed-solomon decoder using two parallel modified evaluator Inversionless Berlekamp-Massey

Abstract

This paper proposes a low power high throughput Reed Solomon decoder designed optimally for handheld devices under the DVB-H standard. This architecture based on Decomposed Inversionless Berlekamp-Massey Algorithm (DiBM), where the error locator and evaluator polynomial can be computed serially. In the proposed architecture, a new scheduling of 6 Finite Field Multipliers (FFMs) is used to calculate the error locator polynomial in a two parallel way and these multipliers are reused to calculate the error evaluator polynomial in a novel architecture called two parallel modified evaluator decomposed inversionless Berlekamp-Massey (MEDiBM) to achieve low energy. This architecture is tested in a pipelined two parallel decoder. This decoder has been implemented by 0:13μm CMOS IBM standard cells for RS(204; 188) and gave gate count of 33K and area of 1:06mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Simulation results show this approach can work successfully at the data rate 100Mbps with power dissipation of 0:266mW.