Low complexity successive cancellation list decoding of U-UV codes

Polar codes are of great interests because they provably achieve the capacity of both discrete and continuous memoryless channels while having an explicit construction. Most existing decoding algorithms of polar codes are based on bit-wise hard or soft decisions. In this paper, we propose symbol-decision successive cancellation (SC) and successive cancellation list (SCL) decoders for polar codes, which use symbol-wise hard or soft decisions for higher throughput or better error performance. First, we propose to use a recursive channel combination to calculate symbol-wise channel transition probabilities, which lead to symbol decisions. Our proposed recursive channel combination also has a lower complexity than simply combining bit-wise channel transition probabilities. The similarity between our proposed method and Arikan's channel transformations also helps to share hardware resources between calculating bit- and symbol-wise channel transition probabilities. Second, a two-stage list pruning network is proposed to provide a trade-off between the error performance and the complexity of the symbol-decision SCL decoder. Third, since memory is a significant part of SCL decoders, we propose a pre-computation memory-saving technique to reduce memory requirement of an SCL decoder. Finally, to evaluate the throughput advantage of our symbol-decision decoders, we design an architecture based on a semi-parallel successive cancellation list decoder. In this architecture, different symbol sizes, sorting implementations, and message scheduling schemes are considered. Our synthesis results show that in terms of area efficiency, our symbol-decision SCL decoders outperform both bit- and symbol-decision SCL decoders.

Combined with cyclic redundancy check (CRC), SC list (SCL) decoder can achieve outstanding error correction performance, which is more obvious with increasing list size. However, the corresponding decoding complexity and latency increase with the list size. To this end, the selection of list size becomes essential for practical applications. A new artificial neural network (ANN) based framework is proposed in this paper to design a hardware-friendly adaptive SCL (DL-ASCL) decoder. First, the list size at each stage is predicted by an ANN predictor. The performance achieved based on the proposed DL-ASCL algorithm is close to the optimal SCL decoder with the same list size, especially in the high signal-to-noise ratio (SNR) region. Meanwhile, the computational complexity is significantly reduced compared with the conventional ones. Numerical results have demonstrated that the proposed deep learning based adaptive SCL decoder can achieve 56% computational complexity reduction compared with the conventional SCL decoder for the polar code with length 128 and rate 1/2. The hardware architecture of the adaptive SCL decoder based on the predicted list size is proposed and the folding technique is also adopted, which helps reduce the hardware cost by about 25%.

Introduction/purpose: The paper introduces a reduced latency stack decoding algorithm of polar codes, inspired by the bidirectional stack decoding of convolutional codes and based on the folding technique. Methods: The stack decoding algorithm (also known as stack search) that is useful for decoding tree codes, the list decoding technique introduced by Peter Elias and the folding technique for polar codes which is used to reduce the latency of the decoding algorithm. The simulation was done using the Monte Carlo procedure. Results: A new polar code decoding algorithm, suitable for parallel implementation, is developed and the simulation results are presented. Conclusions: Polar codes are a class of capacity achieving codes that have been adopted as the main coding scheme for control channels in 5G New Radio. The main decoding algorithm for polar codes is the successive cancellation decoder. This algorithm performs well at large blocklengths with a low complexity, but has very low reliability at short and medium blocklengths. Several decoding algorithms have been proposed in order to improve the error correcting performance of polar codes. The successive cancellation list decoder, in conjunction with a cyclic redundancy check, provides very good error-correction performance, but at the cost of a high implementation complexity. The successive cancellation stack decoder provides similar error-correction performance at a lower complexity. Future machine-type and ultra reliable low latency communication applications require high-speed low latency decoding algorithms with good error correcting performance. In this paper, we propose a novel decoding algorithm, inspired by the bidirectional stack decoding of classical convolutional codes, with reduced latency that achieves similar performance as the classical successive cancellation list and successive cancellation stack decoding algorithms. The results are presented analytically and verified by simulation.

BMERA or convolutional polar codes are an extension of polar codes with a provably better error exponent than polar codes. A successive cancellation (SC) decoding algorithm for BMERA codes similar to SC polar decoders is introduced. A pseudocode description of the SC decoder that can be extended to SC list (SCL) decoding is provided. Simulation results with and without outer CRC codes under SC and SCL decoding are presented for QAM modulation over the AWGN channel to compare the performance of polar and BMERA codes. BMERA codes outperform polar codes by more than 0.5 dB under SCL decoding without outer CRC codes.

As improved versions of the successive cancellation (SC) decoder, the adaptive SC list (SCL) decoder and the segmented CRC-aided SCL (SCA-SCL) decoder can achieve notable complexity reduction compared to the traditional SCL one. However, the former only shows good reduction in high SNR region whereas the latter only works good in low SNR region. To this end, two novel efficient adaptive SCL decoding schemes are proposed to achieve good complexity reduction in both low and high SNR regions. The first one is adaptive SCA-SCL (ASCA-SCL) decoder, which is based on SCA-SCL but with varying list size. The second one is adaptive switching SCL (AS-SCL) decoder, whose list reduction metric switches with regarding to specific SNR value. Numerical results have shown that for (1024, 512) polar code and list size L = 2, compared to the state-of-the-art decoder, the proposed ASCA-SCL decoder and AS-SCL decoder can achieve up to 45.40% and 32.39% computational complexity reduction respectively, while keeping the similar decoding performance.

This paper investigates the transmission of grey scale images encoded with polar codes and de-coded with successive cancellation list (SCL) decoders in the presence of additive white Gaussian noise. Po-lar codes seem a natural choice for this application be-cause of their error-correction efficiency combined with fast decoding. Computer simulations are carried out for evaluating the influence of different code block lengths in the quality of the decoded images. At the encoder a default polar code construction is used in combination with binary phase shift keying modulation. The results are compared with those obtained by using the clas-sic successive cancellation (SC) decoding introduced by Arikan. The quality of the reconstructed images is assessed by using peak signal to noise ratio (PSNR) and the structural similarity (SSIM) index. Curves of PSNR and SSIM versus code block length are presented il-lustrating the improvement in performance of SCL in comparison with SC.

The successive cancellation list (SCL) decoding is used to achieve good error-correcting performance for practical finite-length polar codes. However, the metric sorting that is repeatedly performed in SCL decoding increases the overall decoding latency as the list size increases, making it difficult to apply the SCL decoding to the applications with limited processing time. To reduce the latency of the metric sorting, this paper proposes a new sorting method derived by analyzing path extension cases encountered in SCL decoding. The proposed method can avoid unnecessary sorting operations by adaptively determining the sorting size, and can be combined with other metric sorting methods. Simulation results show that the proposed method significantly reduces the decoding latency for various list sizes and code rates without degrading the error-correcting performance. The proposed method also becomes more effective as the code rate or the list size increases. Combined with the state-of-the-art sorting method, the proposed method reduces the average SCL decoding latency for a (1024, 512) polar code by 33.1% when the list size is 8.

Concatenation of polar codes with cyclic redundancy check (CRC) codes, together with successive cancellation list (SCL) decoding, is known to be an effective approach that can significantly enhance the performance of the original polar codes. Most of the studies on the concatenation of CRC and polar codes, however, pay little attention to the structure of CRC codes themselves, even though the longer CRC may lead to loss in terms of information rate. In this work, we investigate the effect of CRC length on the CRC-concatenated polar code performance by developing an analytical bound for the frame error rate (FER) after the CRC-assisted list decoding. As a result, we reveal that there is a trade-off between the CRC length and FER performance, and for a given target FER, there is the minimum length of CRC that satisfies the FER constraint in high signal-to-noise ratio (SNR). The validity of our analytical framework is confirmed by extensive simulation over an additive white Gaussian noise (AWGN) channel. The results thus offer a useful guideline when designing CRC codes for polar codes with SCL decoding.

Polar codes have recently attracted significant attention due to their excellent error-correction capabilities. However, efficient decoding of Polar codes for high throughput is very challenging. Beyond 5G, data rates towards 1Tbit/s are expected. Low complexity decoding algorithms like Successive Cancellation (SC) decoding enable such high throughput but suffer on errorcorrection performance. Polar Successive Cancellation List (SCL) decoders, with and without Cyclic Redundancy Check (CRC), exhibit a much better error-correction but imply higher implementation cost. In this paper we in-depth investigate and quantify various trade-offs of these decoding algorithms with respect to error-correction capability and implementation costs in terms of area, throughput and energy efficiency in a 28nm CMOS FD-SOI technology. We present a framework that automatically generates decoder architectures for throughputs beyond 100Gbit/s. This framework includes various architectural optimizations for SCL decoders that go beyond State-of-the-Art. We demonstrate a 506Gbit/s SCL decoder with CRC that was generated by this framework.

This paper focuses on low complexity successive cancellation list (SCL)\ndecoding of polar codes. In particular, using the fact that splitting may be\nunnecessary when the reliability of decoding the unfrozen bit is sufficiently\nhigh, a novel splitting rule is proposed. Based on this rule, it is conjectured\nthat, if the correct path survives at some stage, it tends to survive till\ntermination without splitting with high probability. On the other hand, the\nincorrect paths are more likely to split at the following stages. Motivated by\nthese observations, a simple counter that counts the successive number of\nstages without splitting is introduced for each decoding path to facilitate the\nidentification of correct and incorrect path. Specifically, any path with\ncounter value larger than a predefined threshold \\omega is deemed to be the\ncorrect path, which will survive at the decoding stage, while other paths with\ncounter value smaller than the threshold will be pruned, thereby reducing the\ndecoding complexity. Furthermore, it is proved that there exists a unique\nunfrozen bit u_{N-K_1+1}, after which the successive cancellation decoder\nachieves the same error performance as the maximum likelihood decoder if all\nthe prior unfrozen bits are correctly decoded, which enables further complexity\nreduction. Simulation results demonstrate that the proposed low complexity SCL\ndecoder attains performance similar to that of the conventional SCL decoder,\nwhile achieving substantial complexity reduction.\n

Motivated by the significant performance gains which polar codes experience under successive cancellation list decoding, their scaling exponent is studied as a function of the list size. In particular, the error probability is fixed, and the tradeoff between the block length and back-off from capacity is analyzed. A lower bound is provided on the error probability under $\rm MAP$ decoding with list size $L$ for any binary-input memoryless output-symmetric channel and for any class of linear codes such that their minimum distance is unbounded as the block length grows large. Then, it is shown that under $\rm MAP$ decoding, although the introduction of a list can significantly improve the involved constants, the scaling exponent itself, i.e., the speed at which capacity is approached, stays unaffected for any finite list size. In particular, this result applies to polar codes, since their minimum distance tends to infinity as the block length increases. A similar result is proved for genie-aided successive cancellation decoding when transmission takes place over the binary erasure channel, namely, the scaling exponent remains constant for any fixed number of helps from the genie. Note that since genie-aided successive cancellation decoding might be strictly worse than successive cancellation list decoding, the problem of establishing the scaling exponent of the latter remains open.

Successive cancellation list (SCL) decoder has high decoding performance but also require great resource consumption. In this paper, we combine the SCL decoder and the critical set to form a new decoder, which can stably reduce the number of operations by 65% <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\sim$</tex> 70% and maintain similar decoding performance to SCL decoder. The reduction in resource consumption depends only on the arrangement of unfrozen bit sequences, not on the quality of the channel. We also propose to combine this new decoder with adaptive algorithms. In this way, the decoding performance of the decoder can be improved beyond SCL decoders without increasing resource consumption.

Due to the low-latency and high-reliability requirements of 5G, low-complexity node-based successive cancellation list (SCL) decoding has received considerable attention for use in 5G communications systems. By identifying special constituent codes in the decoding tree and immediately decoding these, node-based SCL decoding provides a significant reduction in decoding latency compared to conventional SCL decoding. However, while there exists many types of nodes, the current node-based SCL decoders are limited by the lack of a more generalized node that can efficiently decode a larger number of different constituent codes to further reduce the decoding time. In this paper, we extend a recent generalized node, the sequence repetition (SR) node, to SCL decoding, and describe the first implementation of an SR-List decoder. By merging certain SR-List decoding operations and applying various optimizations for 5G New Radio (NR) polar codes, our optimized SR-List decoding algorithm increases the throughput by almost <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\bm {2\times }$</tex-math></inline-formula> compared to a similar state-of-the-art node-based SCL decoder. We also present our hardware implementation of the optimized SR-List decoding algorithm which supports all 5G NR polar codes. Synthesis results show that our SR-List decoder can achieve a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$2.94 \,\mathrm{Gbps}$</tex-math></inline-formula> throughput and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$6.70 \,\mathrm{Gbps}\mathrm{m}^{-1}\,\mathrm{m}^{2}\,$</tex-math></inline-formula> area efficiency for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\bm {L=8}$</tex-math></inline-formula> .

In this research, a new effective signal processing scheme is proposed for a two-dimensional magnetic recording (TDMR) system using bit-patterned media (BPM). The proposed signal processing scheme uses concatenated cyclic redundancy check polar (CRC-polar) codes [1] as modulation codes and a non-binary low-density parity-check (LDPC) code as an error-correction code (ECC). In decoding process, successive-cancellation list (SCL) decoders [1] are introduced. These SCL decoders are expected to give an error rate performance improvement to the successive cancellation decoder of [2]. In these list decoder, several decoding paths are considered concurrently at each decoding stage. At the end of the decoding process, the most likely path among these survived paths is selected as the single codeword at the decoder output.

In order to achieve a magnificent error-correcting performance Successive Cancellation List (SCL) decoding is a powerful and excellent method which considers L decoding paths at each decoding stage concurrently. However, the conventional SCL decoder uses L copies of Successive Cancellation (SC) decoder for a list size of L thereby resulting in a massive increase in the hardware as the list size increases which is one of the major drawbacks of SCL decoder. One more drawback of SCL decoder architecture is the long latency of the architecture. Using the proposed efficient utilization of existing hardware architecture, there is a reduction in the number of Merged Processing Elements (MPE) by 39% for a list size of 2 and 45% for a list size of 4 when compared to the existing architectures and a vast reduction compared to conventional SCL decoder. The partial pipelining considered in this work can reduce the latency compared to conventional SCL multi-bit architecture to a greater extent.