Abstract
A systematic approach to the optimization of multirate filter bank (MFB) structures is introduced. The approach is based on the multirate signal flow graph (MSFG) representation and transforms. It has the advantages of presenting clear structural information and is free of tedious mathematical manipulations. Another issue discussed is the mapping of a demultiplexer structure onto VLSI architecture with low complexity and low power consumption. This is achieved by modeling the space, power, and processing-speed complexities of VLSI in a multirate environment and applying optimization techniques to search for acceptable solutions. Design examples are given to show the effectiveness of the proposed methods. (Author)
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