Location Effects of Extended Defects on Electrical Properties of p+‐n Junction

Abstract

Ion implantation damage that transforms to crystallographic defects such as dislocation loops or stacking faults with heat‐treatments is unavoidable in VLSI device fabrication. Dislocation loops were introduced into three different regions of p+‐n junction such as the p+, the depletion, or the n region by Si implantation followed by annealing. Stacking faults were introduced into the p+ region or extended into the depletion region of p+‐n junction by Si implantation followed by oxidation. Locations, densities, and characteristics of the extended defects were scrutinized with transmission electron microscopy (TEM). In forward bias, diodes having dislocation loops still show diffusion currents with the ideality factor equal to 1, regardless of their locations, only increasing the ohmic resistance at forward bias higher than 0.5V. In addition, dislocation loops in the depletion or the n region caused higher diffusion current levels than control diodes which did not have dislocation loops. In reverse bias, dislocation loops in the n region caused the smaller generation current than those in the depletion region, whereas dislocation loops in the p+ region caused current levels as low as control diodes. Stacking faults in the p+ region functioned similarly to dislocation loops in the p+ region except for showing higher ohmic resistance than dislocation loops, even though the densities of the former were much lower than those of the latter. Only stacking faults extending into the depletion region caused the large leakage currents which degrade the diode functions.