Abstract
Lightweight devices usually come with an additional cryptographic co-processor for enabling the secrecy, in contrast, the master processor is typically a commercial processor where the required protection mechanism is missing. In this paper, an on-going effort in secured architecture named S-RISC-V based on RISC-V core is introduced. The mechanism of key generation used for memory protection is supported together with the joint efforts in the following perspectives, including ISA extension, compiler improvement, and hardware implementation. The architecture has been verified on Zedboard running at 25MHz, driven by the host ARM core. The area overhead is less than 10%, compared with the original RISC-V core.
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