LBDR3D: Fault tolerant routing scheme for 3D NoCs

Abstract

The reliable and scalable design for Network on chips (NoCs) usually uses mesh topologies. But the increase of the number of cores integration on a single chip increases network diameter and introduces power and area constraints in designing system-on-chips. Thus 3D NoCs an alternating interconnect technology has been introduced which sustains growth and performance with increased cores integration. But 3D NoCs faces fault issues due to fabrication defects, component failures, power saving schemes, heterogeneous cores and technology integration on different layers which may lead to irregular topologies. Thus to design efficient routing algorithms for such irregular 3D NoCs becomes a challenge. This paper provides Logic Based Distributed Routing for 3D NoCs (LBDR3D) which extend the capabilities of Logic Based Distributed Routing of 2D NoCs for handling faults in 3D NoCs. The Logic Based Distributed Routing is topology agnostic in nature and works efficiently for handling faults in 2D mesh topology but fails to work in 3D NoCs. The paper provides a new circuit LBDR3D that provides routing implementation and eliminates the need of routing tables for routing and handling faults in regular 3D mesh NoCs. Experimental results show that LBDR3D mimic the performance of 3D NoCs routing algorithms and provide fault tolerance without any routing tables.