Lateral and Vertical Gate Oxide Stacking Impact on Noise Margins and Delays for the 8T SRAM Designed With Source Pocket Engineered GaSb/Si Heterojunction Vertical TFET: A Reliability Study

Manas Ranjan Tripathy,Satyabrata Jit

doi:10.1109/tdmr.2021.3098437

Manas Ranjan Tripathy, Satyabrata Jit

Open Access

https://doi.org/10.1109/tdmr.2021.3098437

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Abstract

This work investigates the impact of gate-oxide stacking on the performance of source-pocket engineered (SPE) GaSb/Si heterojunction (HJ) vertical TFETs (VTFETs) based 8T SRAMs. The 8T SRAMs circuits are designed using the SPE-HJ-VTFETs with three different gate-oxide engineered structures: laterally stacked HfO 2 /Al 2 O 3 gate-oxide, vertically stacked Al 2 O 3 /HfO 2 gate-oxide and only Al 2 O 3 as gate-oxide. The surface potential, electric field, transfer characteristics, drain characteristics and intrinsic capacitances of all three types of VTFETs considered in this paper are compared. The read static noise margin (RSNM), write margin (WM), read delay as well as write delay of the SRAMs designed by three forms of the SPE GaSb/Si HJ-VTFETs structures have been compared. It is shown that the intrinsic capacitances originated from different stacking-based gate-oxide structures affect the performance of the SRAM significantly. The read delay is significantly the highest for the 8T SRAM designed by laterally stacked gate-oxide based SPE-HJ-VTFETs than the other two 8T SRAMs under consideration. Electrical performance analysis of the VTFETs under study has been studied using commercially available SILVACO ATLAS TCAD tool whereas performance analysis of the 8T SRAMs have been carried out utilizing CADENCE Virtuoso tool by virtue of Verilog A code.

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