Large-area CMOS SPADs with very low dark counting rate

Abstract

We designed and characterized Silicon Single-Photon Avalanche Diodes (SPADs) fabricated in a high-voltage 0.35 μm CMOS technology, achieving state-of-the-art low Dark Counting Rate (DCR), very large diameter, and extended Photon Detection Efficiency (PDE) in the Near Ultraviolet. So far, different groups fabricated CMOS SPADs in scaled technologies, but with many drawbacks in active area dimensions (just a few micrometers), excess bias (just few Volts), DCR (many hundreds of counts per second, cps, for small 10 μm devices) and PDE (just few tens % in the visible range). The novel CMOS SPAD structures with 50 μm, 100 μm, 200 μm and 500 μm diameters can be operated at room temperature and show DCR of 100 cps, 2 kcps, 20 kcps and 100 kcps, respectively, even when operated at 6 V excess bias. Thanks to the excellent performances, these large CMOS SPADs are exploitable in monolithic SPAD-based arrays with on-chip CMOS electronics, e.g. for time-resolved spectrometers with no need of microlenses (thanks to high fillfactor). Instead the smaller CMOS SPADs, e.g. the 10 μm devices with just 3 cps at room temperature and 6 V excess bias, are the viable candidates for dense 2D CMOS SPAD imagers and 3D Time-of-Flight ranging chips.