Ka-band low noise amplifier using standard 0.18 [micro sign]m CMOS technology

Abstract

A low-power-consumption (26.93 mW) 32 GHz (Ka-band) low noise amplifier (LNA) using standard 0.18 µm CMOS technology is reported. To achieve sufficient gain, this LNA is composed of three cascaded common-source stages. The output of each stage is loaded with a bandpass (or a highpass) combination of L and C to provide parallel resonance, i.e. to maximise the gain, at the design frequency. This LNA achieved input return loss (S11) of −13.3 dB, output return loss (S22) of −13.4 dB, forward gain (S21) of 10.2 dB and reverse isolation (S12) of −19.1 dB at 32 GHz. This LNA consumed only a small DC power of 26.93 mW. The chip area is only 740×500 µm, excluding the test pads.