Abstract
This paper presents a method for functional test generation, which aims self-test of RISC processors and processor cores. The method allows developing compact and quite effective software based tests if only the instruction set architecture (ISA) or ISA together with some micro architecture features are known. We have successfully applied this methodology to test a RISC processor core
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.