IP Core Identification in FPGA Configuration Files using Machine Learning Techniques

Abstract

In modern day industry and scientific research, pertaining to experimental scenarios, real world applications or consumer electronics, Field Programmable Gate Arrays (FPGAs) are becoming a popular choice. The very distinctive nature of FPGAs enables reconfigurability, scalability and adaptivity of the associated embedded design which makes it a remarkable alternative to traditional hardware. An FPGA is able to dynamically reconfigure itself during run-time, entirely or partially, by way of unloading and loading bitstreams. In this paper, an approach is introduced to analyze and inspect FPGA bitstreams by making use of supervised machine learning. By exploiting machine learning, we demonstrate how neural networks can be trained to identify and trace a certain hardware module or an IP core (Intellectual Property core) with some known functionality in FPGA bitstreams. We perform an analysis of FPGA bitstreams by incorporating Artificial Neural Networks (ANNs) based classification ranging from Multiple Layer Perceptrons (MLPs) or to modern Convolutional Neural Networks (CNNs).