(Invited) Energy Efficient Transistors with 2D Materials

Abstract

Emerging two-dimensional materials provide new opportunities to design post-Moore’s Law devices due to their atomically thin dimensions, layer dependent band gaps and effective masses, large density of states, and exotic band structures. Novel designs for energy efficient steep subthreshold swing transistors are investigated in 2D materials, highlighting the material and device properties that optimize the metrics needed to compete with CMOS. Based on atomistic non-equilibrium Green’s function simulations, the device characteristics of various 2D material tunnel field effect transistors (TFET) [1] are compared. Since chemical doping of 2D materials is still a challenge, we outline design considerations for generating electrostatic p-n junctions. Since low On-currents are a major challenge in TFETs, we show how On-currents and energy-delay products can be improved significantly in both chemically and electrically doped 2D TFETs. We also present a new design for an electrically doped 2D TFET, which uses a combination of high and low k dielectrics to achieve high On-currents [2]. We also highlight that the material properties of few-layer Phosphorene/Black Phosphorus make it an ideal candidate for low power TFETs. To replace CMOS transistors, TFETs need to achieve simultaneous supply voltage and channel length scaling. We show how the performance of a TFET degrades as the channel length is scaled. To solve this issue, effective masses and bandgaps need to be engineered according to some predicted conditions. We show that 2D materials such as Phosphorene help channel length scaling in TFETs compared to III-V TFETs. We also propose a novel design for a Phosphorene TFET using an L-shaped gate, which utilizes the large anisotropic effective mass of Phosphorene to improve On-currents and to suppress Off-state leakage [3]. Such a TFET also helps channel length scaling down to 2nm channels [4]. This research is supported by Semiconductor Research Corporation’s LEAST center. H. Ilatikhameneh et al, IEEE J-EDS Vol. 4, Issue 5, 260-265 (2016).H. Ilatikhameneh et al, IEEE EDL Vol. 36, No. 10, 1097-1100 (2015).T. A. Ameen et al, Scientific Reports 6, 28515 (2016).H. Ilatikhameneh et al, Scientific Reports 6, 31501 (2016). Figure 1 a) Design of an L-shaped gate in a Phosphorene TFET. b) The current-voltage characteristics of planar gates along armchair and zigzag directions compared to that of the L-shaped gate. Figure 1