(Invited) Characterization of Group IV Based Nanowires Manufactured on Advanced Engineered Substrates

Abstract

Advanced substrate engineering is gaining new applications for nano-scaled devices where such substrates offer unique possibility to tailor the strain and the carrier transport. In general, XOI is a notation for wafers with a semiconductor-on-insulator where X is any alloy from SiGeSnC materials or III-V compounds. In special, strained XOI substrates (s-XOI) are widely used to manufacture nanowire transistors where the carrier mobility is enhanced by strain. So far, wafer bonding or condensation methods have been applied to manufacture XOI wafers. In case of SiGe-on-insulator (SGOI), a thin SiGe layer is grown on SOI and subsequently oxidized to create a single SiGe layer on oxide. During oxidation the Si atoms are preferably consumed and Ge atoms are driven toward the oxide box acting as a diffusion barrier. Therefore SGOI wafers suffer from point defects which have a strong influence on the carrier mobility, thermal conductivity and even optical properties. Post annealing may improve the layer quality and majority of the defects could be disappeared. The wafer bonding is more complicated and sensitive method. This relates to the requirements e.g. surface flatness, layer quality of the semiconductor and the amount of exerting bonding force. In manufacturing of Ge-on-insulator wafers, a high quality Ge layer is grown at 700-750 °C on a low quality Ge (grown at 300-400 °C). The Ge layers are transferred and bonded to oxide wafers by using a uniform force of few kNs. Afterwards, the wafers are annealed at 500-600 °C before etch back step (see Fig.1). It is important to mention here that the annealing step has to be decreased for bonding of GeSn-on-insulator wafers in order to avoid strain relaxation. In this work, manufacturing methods for different sizes of XOI and s-XOI wafers are presented and an attention is paid for using the manufactured XOI wafers for the thermoelectric application, where lateral nanowires are formed. As an example, for SiGe nanowires the seebeck coefficient is enhanced in presence of defects, however, any kind of defects in XOI wafers degrade the channel mobility in the processed MOSFETs. Characterization techniques e.g. high-resolution reciprocal maps using synchrotron x-ray beam, high resolution transmission electron microscopy, and photoluminescence were applied to detect the defects and estimate the strain relaxation. The experimental data is linked to explain the electrical properties of XOI wafers and finally to nanowires and MOSFETs. Figure 1