Abstract
Gallium nitride is becoming more popular in low-voltage applications. Gallium nitride (GaN) high electron mobility transistors (HEMTs) has positive temperature feature. It makes parallel application feasible for GaN HEMTs. Meanwhile, paralleled GaN HEMTs will increase the power handling capability and the efficiency of the converter. The parasitic parameters of both driving and power loop layout are critical which need to be equalized and minimized in GaN HEMT parallel operation. The parameters mismatch of the parallel branch will lead to significant effect on the dynamic characteristics and bring thermal problem of the GaN HEMTs. This paper focuses on the design of paralleled low-voltage enhancement GaN HEMT, and evaluates the effect of the parasitic inductances in both driver and power loops. The LT-spice and ANASYS Q3D Extractor simulation are carried out to analysis the effect of the unbalance parameters. The design guidelines for driver and PCB design are summarized as well. Finally, a 300W isolated DC-DC converter is built to verify the analysis and simulation on parallel operation.
Highlights
The newly wide bandgap (WBG) semiconductors, especially Gallium Nitride (GaN) high electron mobility transistors (HEMTs), have more potentials to feature with higher operating frequency, lower on-state resistance and higher temperature capability compared with Si device [1]–[4]
We focused on the design of low voltage enhancement GaN HEMTs in parallel connection, and evaluated the effect of the parasitic inductances in both power and driving loops, especially the unbalancing of the paralleled branch
The influence of temperature on the threshold voltage is another key factor in parallel application of GaN HEMTs
Summary
The newly wide bandgap (WBG) semiconductors, especially Gallium Nitride (GaN) high electron mobility transistors (HEMTs), have more potentials to feature with higher operating frequency, lower on-state resistance and higher temperature capability compared with Si device [1]–[4]. We focused on the design of low voltage enhancement GaN HEMTs in parallel connection, and evaluated the effect of the parasitic inductances in both power and driving loops, especially the unbalancing of the paralleled branch. We design two low-voltage enhancement GaN HEMTs (EPC2010) in parallel implementations in the microinverter to achieve the power level. The influence of temperature on the threshold voltage is another key factor in parallel application of GaN HEMTs. Fig.1(b) shows the normalized threshold voltage Vth VS. Equivalent model of the enhancement GaN HEMTs. and the threshold voltage of paralleling devices will be equal. It can be concluded that the enhancement GaN HEMTs is suitable for parallel applications for the positive temperature coefficient of the threshold voltage
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