Investigation of LVTSCR ESD protection devices with RC-INV triggering circuits

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Abstract Two series of electrostatic discharge (ESD) protection devices, based on the N-type and P-type Low Voltage Triggering Silicon-Controlled Rectifier (LVTSCR) structure, were designed and fabricated in a 0.25 μm Bipolar-CMOS-DMOS process. The same trigger circuit, consisting of a resistor, capacitor, and inverter, connected to various current injection points in NLVTSCR and PLVTSCR, is designed to respectively lower the trigger voltage (V t1) in RCINV_NLVTSCR and improve the latch-up immunity in RCINV_PLVTSCR. To investigate the impact of additional trigger circuit in LVTSCRs, transient device simulations are performed to elucidate the operational mechanism during ESD events, while the Transmission Line Pulse measurement system is employed to evaluate the devices’ ESD protection capabilities. The results show that the trigger voltage decreases when the external trigger circuit provides additional trigger current into the base region of parasitic transistors in RCINV_NLVTSCR, enabling its usage for the 5 V power-rail ESD protection. The high double-snapback trigger current is obtained as the trigger circuit hinders the formation of the primary SCR discharge path in RCINV_PLVTSCR, improving its latch-up immunity.