Investigation of low growth temperature AlGaAs and GaAs using metal–insulator–semiconductor diagnostic structures

Abstract

GaAs and Al0.3Ga0.7As layers grown by molecular-beam epitaxy (MBE) at 250 °C and incorporated as the gate insulators in metal–insulator–semiconductor (MIS) structures are examined using capacitance–voltage and current–voltage techniques. Samples which are not annealed, and samples annealed for 10 and 20 min under an arsenic ambient at 600 °C are examined. MIS structures using material grown at low temperatures without annealing are found to be extremely leaky at room temperature due to a high defect concentration. For unannealed samples and samples annealed for 10 min, a deep level trap is found to be the source of free carriers in the low growth temperature layer. Capacitance–voltage profiling can be accomplished on both structures, indicating the Fermi level is weakly pinned in these structures. For samples annealed for 20 min, however, no modulation of the device capacitance is possible, and the layer exhibits extremely high resistivity. This indicates that the Fermi level is pinned strongly in samples annealed for 20 min, possibly due to the precipitation and/or interfacial segregation of metallic arsenic.