International Roadmap for Failure Analysis

Longitudinal crack failure analysis of box of S135 tool joint in ultra-deep well

With the continuous development of manufacturing technology, the integration and accuracy of integrated circuits are getting higher and higher, and the requirements of fault analysis technology are also getting higher and higher. In the past, the traditional failure analysis technologies could not meet the requirements until the emergence of OBIRCH (Optical Beam Induced Resistance Change) failure location technology. OBIRCH technology can accurately locate the failure of the IC, and establish the connection between the failure point and the electrical characteristics. This article will introduce the basic equipment and principle of OBIRCH technology, and show the great role of this technology in integrated circuit failure analysis technology through several actual failure analysis cases.

Failure analysis plays a very important role in the early introduction and fast yield improvement of new generation LSIs. Novel failure analysis technologies have been developed including an expert-system-based memory cell failure cause identification system, MEMOFANEX. These predicted causes are statistically related to the particle or pattern defects monitored at each wafer processing step using the software, MEMOLINK, which can lead to a very effective suggestion of which processing step accounts for the low yield problem. In addition, a novel technology named MEMOFAN has successfully isolated many peripheral circuitry failure locations. For logic LSIs a technology is developed to trace LSI's fault path back to the location of the defect using an electron beam voltage image. With this technique, about 800 logic LSI's have been successfully analyzed, resulting in successful debugging and yield improvement. This paper first makes brief reviews of enhancement technologies, then reviews the recent trends in yield management systems, and finally reports on our systems, putting an emphasis on failure analysis technologies.

The failure analysis of integrated circuits plays a very important role in the improvement of the reliability in communications products. This paper intends to mainly introduce the failure analysis technology and process of integrated circuits applied in the communication products. There are many technologies for failure analysis, include optical microscopic analysis, infrared microscopic analysis, acoustic microscopy analysis, liquid crystal hot spot detection technology, optical microscopic analysis technology, micro analysis technology, electrical measurement, microprobe technology, chemical etching technology and ion etching technology. The integrated circuit failure analysis depends on the accurate confirmation and analysis of chip failure mode, the search of the root failure cause, the summary of failure mechanism and the implement of the improvement measures. Through the failure analysis, the reliability of integrated circuit and rate of good products can improve.

Ball grid array (BGA) is an interconnect technology that smaller package sizes and lower failure rate, which joints are hidden in the body of the device. It is hard to detect the solder joint defects and analyze the failure. How to effective judge the quality and reliability of BGA solder joints is a difficult problem in electronic manufacturing. In this paper the failure analysis process and methods on lead-free BGA solder joints are introduced mainly. Combined with the typical failure analysis case of lead-free BGA, these analysis technology is introduced in the application of actual case. The failure analysis techniques play an important role on promoting the reliability of lead-free BGA solder joints, which can quickly and accurately find the failure cause. It will lay the foundation for improving the quality of products.

The EDFAS Board of Directors (BOD) has undertaken an initiative to help drive the development of failure analysis methods as leading-edge semiconductor technology approaches the sub-20 nm regime. To streamline efforts and leverage existing work, the BOD recently surveyed its constituency to gauge their opinions on the capability gaps identified by the Sematech councils. This article briefly discusses the methodology of the survey and provides a summary of the responses along with key findings.

Great advances in microelectronics failure physics, process reliability, reliability test and evaluation and failure analysis technologies have been achieved in China recently. Some of the significant achievements include the Hot-Carrier Injection (HCI) degradation model, gate oxide TDDB, Negative Bias Temperature Instability (NBTI) of very deep sub-micro(VDSM) devices, process quality parameter monitoring (PM), statistical process control(SPC) technique, wafer-level-reliability engineering of CMOS process, the equivalent thickness method for evaluating quality and reliability of dielectrics in GaAs monolithic microwave circuits (MMICs), reliability evaluation of metallization interconnect, accurate measurement of anti-latch-up characteristics, total dose X-ray radiation evaluation, accelerated lifetime assessment of GaN/GeSi devices, reliability assurance of Known-Good-Dies (KGDs), failure location and micro-defect analysis of ICs, failure diagnosis and design verification, and the failure analysis expert systems.

Recently, miniaturization and three-dimensional integration for improving the performance of electric devices have been accelerated, and smaller storage batteries with higher energy density and shrinked electric components have been more required. Therefore, failure analysis technologies targeted for these cutting-edged devices should be developed for increasing production yields and reducing product accidents. In mass production processes, pre-shipment inspections are performed on the core parts of electronic devices. In the case of electronic parts, energization check is adopted, and in the case of storage batteries, voltage drop, that is called to be an aging test, is checked. However, many cases have been reported in which products, that have passed the inspection, cause accidents. One of the typical causes of failures related about electronic components is internal electric-short caused by foreign matters mixed into the insulation or whiskers accidentally generated from the electrodes and wiring. Similarly, storage batteries also accidentally have internal short circuits due to foreign matter contaminations and dendrite formation at the electrodes. The internal short-circuited points of electronic components and storage batteries are identified by X-ray imaging method. However, it is difficult to acquire the contrast due to the lack of the dynamic range required for visualization of short-circuited parts because the wirings and insulation areas between electrodes have been significantly miniaturized. In addition, short circuits between wirings on the surface of electronic circuit boards have been visualized by thermography, although it is difficult to apply electronic components with multi-layered electrodes.Then we have focused on the relationship between the electric current distribution inside the devices and the magnetic field generated from it and spread toward outside, we have succeeded in deriving the analysis solution of the inverse problem for the first time. Combining this novel theory and a highly-sensitive magnetic field detection based on quantum effect, we have developed a subsurface electric current imaging system capable of detecting electric short-circuited points in the deep region. In this study, we discuss about the details of the theory about the analytical solution of the inverse problem and the visualization system, and show some results of failure analysis for actual electronic components and storage batteries.[1] Yuki Mima, Noriaki Oyabu, Takeshi Inao, Noriaki Kimura, Kenjiro Kimura, “Failure analysis of electric circuit board by high resolution magnetic field microscopy” Proceedings of IEEE CPMT Symposium Japan, pp.257-260, 2013.[2] Kenjiro Kimura, Yuki Mima, Noriaki Kimura, “Local electric current reconstruction theory for nondestructive inspection inside battery cell using magnetic field measurement”, Subsurface Imaging Science & Technology, 1, 1, pp.1-16, 2017.[3] Shogo Suzuki, Hideaki Okada, Kai Yabumoto, Seiju Matsuda, Yuki Mima, Noriaki Kimura, and Kenjiro Kimura, “Non-destructive visualization of short circuits in lithium-ion batteries by a magnetic field imaging system”, Japanese Journal of Applied Physics, Vol 60, No 5, pp.056502-1-4, 2021.

This column reflects on the emergence of integrated fabless manufacturers (IFMs) in the semiconductor industry and the effect it will have on failure analysis. In the IFM environment, FA will likely play the same roles, as in design debug, qualification, yield, and customer returns, but with new challenges and expectations as explained in this guest column.

This article addresses the considerations related to the development and introduction of new materials in response to the increasing performance demands of microelectronic devices, and how these new materials will affect characterization and failure analysis. The article is largely extracted from the “Deprocessing/Inspection White Paper” generated by the SEMATECH Product Analysis Forum (PAF), with updates from the PAF response to the International Technology Roadmap for Semiconductors.

Semiconductor trends as embodied in the International Technology Roadmap for Semiconductors (ITRS) provides a guide for the challenges facing the failure analysis community. The technical challenges fall primarily into two categories: failure site isolation and physical analysis. The failure site isolation challenges are driven primarily by the device complexity and reduced accessibility of circuit nets. Additional challenges arise due to the increase in device operating speed and pin count. The challenges in physical analysis are driven primarily by smaller device feature sizes and by the host of new materials being introduced. In addition to the technical challenges, infrastructure changes are also likely to occur. The likely industry paths for addressing these challenges are discussed. The International Sematech Product Analysis Forum (Joseph et al, 2000) has identified ten primary challenges for the future of the failure analysis in the semiconductor industry: localization and electrical characterization; deprocessing techniques for new materials; system-on-a-chip; imaging of small defects and structures; detection and characterization of nonvisual defects; verification and test; globally dispersed entities as virtual factory; fault isolation and simulation software; cost of failure analysis; complexity and volume of data. These challenges have been correlated to the Technology Working Group Difficult Challenge table in the ITRS.

Failure analysis is a critical element in integrated circuit manufacturing. This paper explores the challenges for IC failure analysis in the environment of present and future silicon IC technology trends, using the 1994 National Technology Roadmap for Semiconductors as a technology guide. Advanced techniques that meet the challenges of state-of-the-art IC technology are described and their applications are discussed. New approaches shall be required for failure analysis to keep pace with future advancements in IC technology.

Integrated circuit (IC) production is critically dependent on characterization and failure analysis (FA) (Ref. 1). Experiment evaluation, technology qualification, yield and reliability learning, and time-to-market are driven by rapid and accurate FA. Testing and fault isolation are essential in identifying electrical faults and in localizing them to regions small enough to be examined by high-resolution electron and scanning-probe microscopes. This presentation introduces IC characterization and failure analysis, discusses their roles in manufacturing, and examines limitations imposed by shrinking features, lower supply voltages, and smaller design margins. R&D needs are also projected based on the CMOS IC technology roadmap (Ref. 1).

The electronics industry faces an explosion of data collection, exchange and storage for the Internet of Everything, cloud computing, and many more applications. A dramatic performance gain of circuits and systems will be required, including a drastic increase of operating frequency, combined with very low power and low latency—all this at no cost increase. Although the International Technology Roadmap for Semiconductors, representing the progress of Moore’s law, edited their final report in 2016, it can easily be predicted that electronic systems and packages will undergo enormous miniaturization and new interconnect concepts involving new materials and solutions, called “heterogeneous integration.” First silicon debug and diagnosis and failure analysis (FA) rely on internal signal tracking using contactless fault isolation (CFI). CFI is performed from the chip backside utilizing near-infrared optical probe that interacts with the logical signal. This paper assesses CFI readiness for the expected evolution on chip level and system/package level. Challenges and new opportunities will be discussed that CFI encounters with 3-D integration and photonic interconnects. Together with innovations in test, reliability, and security, a vision and several options are presented. They indicate how challenges to CFI may be mastered by new concepts of debug and FA, when they are part of the design concept of the electronic systems from early on.

This chapter presents solutions from the International Roadmap for Failure Analysis (IRFA) that address gaps identified in the 2022 Electronic Device Failure Analysis Technology Roadmap. The chapter examines sub-focus areas by analyzing their technical challenges, target outcomes, gap solutions published since the last report, and potential future solutions. The IRFA summary covers multiple domains within die-level isolation and the package innovation roadmap council.